Mity CPU Platforms

07/12/2016

09:02 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

Excellent glad you got it working. Jonathan Cormier

12:16 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

Johnathan,
Joy Joy, Happy Happy.
Everything is working. There were three items altogether. First was the "open... Ian St. John

07/11/2016

05:06 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug

I looked deeper into the error we were provoking on our bench; it turned out to be a c++ vector de-referencing error ... Fred Weiser

09:41 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)

Hi Tom,
As the Root Port, the HPS will control the reset to the PCIe. This can be an HPS GPIO, loaned pin, or FPG... Adam Dziedzic

09:02 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)

After a bit of rearranging, I've gained the use 179 (B8A_RX_T1_N/CLK7n) for the PERSTn. I believe that should work fi... Thomas Carpenter

08:37 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)

Hi Adam,
Thanks, I hadn't realised that restriction was just on CvP. As we don't need that, you say that any IO ca... Thomas Carpenter

08:11 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)

Hi Thomas,
The Cyclone V has a mode where it can be configured using CvP (Config via Protocol) - this configures t... Adam Dziedzic

07/09/2016

10:22 PM MitySOM-5CSX Altera Cyclone V FPGA Development: 5CSX-H6-53B-RC with PCIe Hard IP (Root)

Hi,
We are considering one of the MitySOM boards for use in one of the projects we are working on. I'm currently g... Thomas Carpenter

06:24 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

Ian St. John wrote:
> Can you confirm that the signal marked as 'reserved' just beside the SPI1_CSC1 is the SPI1_CSC... Jonathan Cormier

05:56 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

Hmm. I asked the EE about the diagram and he was interested in the fact that there was a pull up on the CS line. Appa... Ian St. John

12:40 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

The eeprom is on the i2c0 bus. I'm assuming you are talking about the SPI Nor flash which is on SPI1_CS0.+
Oops... Ian St. John

01:23 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug

Hi Fred,
Syslink is newer than DSPlink, though in the context of the L138 it's very similar code (syslink evolved ... Michael Williamson

12:11 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug

The error collected above was on the bench after making some minor software changes seemingly unrelated with the code... Fred Weiser

11:23 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug

I found the following on the TI site; looks like they struggled with this issue with sys-link... I'm not sure how sys... Fred Weiser

07/08/2016

11:55 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: L138 dsplink problem - schedule while atomic bug

I think there may be a bug in the dsplink kernel code that causes the scheduler to run after a call to spinlock. "rem... Fred Weiser

09:33 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

Ian St. John wrote:
> I am building and programming a custom board without Linux. Basic embedded drivers running fro... Jonathan Cormier

07/07/2016

11:26 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: /sys/class/fpga-bridge directory is empty

Thank you for letting us know about this, it was a bug that was caused by some updates to the ethernet driver, which ... Daniel Vincelette

07/05/2016

10:18 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: SPI1 controller, access to FLASH and carrier board. NOT linux based.

I am building and programming a custom board without Linux. Basic embedded drivers running from SPI1,CS0 (8MB NOR Fla... Ian St. John

06/30/2016

11:08 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?

Malcolm,
Thanks for catching the typo, it's been updated.
With the CSEL "properly" set and the module still not... Alexander Block

03:49 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?

Alex,
Thank you for the reply.
I've checked the "gotchas" wiki page and the CSEL setting was the only thing not... Malcolm Hartnell

09:31 AM MitySOM-5CSX Altera Cyclone V Software Development: /sys/class/fpga-bridge directory is empty

I downloaded the latest kernel sources from the critical link repo, rebuilt the kernel and .dtb files, and loaded the... Mike Cherny

06/29/2016

10:01 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?

Malcolm,
Dan and Adam brought this issue to my attention and I will followup concerning the RMA replacement via e-... Alexander Block

05:55 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?

I've tried both suggestions but the result is the same, I get the "CALIBRATION FAILED" message on my first board and ... Malcolm Hartnell

06/28/2016

11:56 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?

Dan,
I've downloaded the file you provided the link for but first ...
Adam,
I presently have CSEL[0-1] set t... Malcolm Hartnell

11:39 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?

There is a CV errata that can cause such a failure. Please check that the CSEL[0-1] pins are set to "00" to avoid a ... Adam Dziedzic

11:13 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?

Hello Malcolm,
I know you said that your current SD card works for one of your SOMs but would you mind trying our ... Daniel Vincelette

11:00 AM MitySOM-5CSX Altera Cyclone V Software Development: Why do I get a "CALIBRATION FAILED" error during boot?

I have been using the same module for the last two weeks and today it has started giving the "CALIBRATION FAILED" err... Malcolm Hartnell

06/24/2016

01:10 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Building BSP for 5cse

Hi Sam,
I've been able to recreate what you're seeing. It looks like the devicetree generated through yocto is nam... Daniel Vincelette

06:41 AM MitySOM-5CSX Altera Cyclone V PCB Development: RE: Development Kit 2.5V VIO, change to 3.0 or 3.3

Thank you Alex, that's exactly what I wanted to know. I understand your point about the warranty, and proceeding car... Stephen Snyder

06/23/2016

04:47 PM MitySOM-5CSX Altera Cyclone V PCB Development: RE: Development Kit 2.5V VIO, change to 3.0 or 3.3

Stephen,
Thanks for reaching out to us about this question.
Please note that making any modification to the car... Alexander Block

09:56 AM MitySOM-5CSX Altera Cyclone V PCB Development: Development Kit 2.5V VIO, change to 3.0 or 3.3

It looks like banks 3B, 4A, and 8A have their I/O voltage tied to a 2.5V supply on the development kit.
If I want ... Stephen Snyder

12:32 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Building BSP for 5cse

Hi Sam,
I'm currently re-running the yocto build here to see if I can recreate the issue you are seeing. I will up... Daniel Vincelette

11:36 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Building BSP for 5cse

Hi Alex,
I selected the 5cse for the build, not the 5csx. I have done this full build no fewer than 3 times with ... Sam Anderson

11:17 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Building BSP for 5cse

Sam,
I believe that the issue you ran into if following the Yocto wiki steps is that you may have selected the "mi... Alexander Block

06/22/2016

07:49 PM MitySOM-5CSX Altera Cyclone V Software Development: Building BSP for 5cse

I am trying to follow your documentation for using Yocto to build an image for the 5CSE on the dev board carrier, and... Sam Anderson

04:13 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: kernel 3.2 - tcpip stack latency

Hi Greg,
Than you for your feedback.
Indeed, flag CONFIG_PREEMPT is set in kernel config. As far as we can see... Patrice Bastiaens

06/21/2016

01:30 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: kernel 3.2 - tcpip stack latency

Hi Patrice,
Since you are using SCHED_RR I am assuming you are using CONFIG_PREEMPT in your kernel config, correc... Gregory Gluszek

06:26 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: kernel 3.2 - tcpip stack latency

Hello,
We've built an application receiving messages from two devices at a rate of 1 message of 1440 bytes every 1... Patrice Bastiaens

03:45 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: How to add aditional HPS GPIO's

Hi Alex,
Still a few misnumbered things in the above post.
Anyway, removing the switches from the DTS means tha... Matthew Schubert

06/20/2016

01:15 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output and Quartus Versions

Steve,
We have successfully rebuilt the "HDMI example":https://support.criticallink.com/redmine/projects/5csxbase/... Alexander Block

11:07 AM MitySOM-5CSX Altera Cyclone V FPGA Development: HDMI Output and Quartus Versions

Hi,
I noticed that the HDMI Output example you've posted was done in Quartus 15.1 but the VM with the toolchain in... Stephen Snyder

01:10 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: How to add aditional HPS GPIO's

Maetthew,
Good catch. Apparently when I did the mapping I started off by one. We have updated the post above to ha... Alexander Block

02:09 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: How to add aditional HPS GPIO's

I have noticed that in the DTS the switches are now on the GPIOs that I want to use:
http://support.criticallink.com... Matthew Schubert

06/19/2016

11:26 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: How to add aditional HPS GPIO's

I'm having some issues setting GPIO37, 40 and 41 from within Linux.
Firstly, in the instructions above, you mentio... Matthew Schubert