Activity
From 01/20/2017 to 02/18/2017
02/17/2017
- JC 02:00 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Problems building the Kernel
- Your right I can't find the u-boot-tools archive anymore.
Luckily the mkimage tool is built by u-boot. So it can be copied to the system so its available in the path.
Instructions partially from https://support.criticallink.com/red... - HB 01:39 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Problems building the Kernel
- Hi Jonathan,
We followed the instructions in the link, but we continue having problems to get the U-boot-tools package, it updated some other things, but we got this error:
*W: Failed to fetch http://ppa.launchpad.net/u-boot-tool... - JC 12:34 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Problems building the Kernel
- We are working on releasing new versions of the VM. In the mean time you can change the repos so they point to the "old-releases".
http://askubuntu.com/questions/91815/how-to-install-software-or-upgrade-from-an-old-unsupported-release?... - Hi all,
I´m trying to do the "FPGA GPIO Core Example":https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Device_Drivers#FPGA-GPIO-Core-Example
In the step #1 "Load an FPGA image with a GPIO core componen... - JC 12:32 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: MitySOM_335x VIO_1P8 Tolerance
- Its mode pin is grounded.
- JC 12:31 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: MitySOM_335x VIO_1P8 Tolerance
- The VIO_1P8 is driven by a TPS62290DRVT regulator. See here http://www.ti.com.cn/cn/lit/ds/symlink/tps62290.pdf
-
12:09 PM
MitySOM-335x (ARM Cortex-A8 Based Products)
PCB Development: MitySOM_335x VIO_1P8 Tolerance
- What is the range of voltages (tolerance) on the VIO_1P8 output supply on the SOM. We are using it as the VREFP for the ADC?
02/15/2017
- Hello, good day,
I am working with the MitySOM-1810F PROFIBUS Development kit which includes the AM1810 ARM Microprocessor For PROFIBUS and Spartan 6, I would like to implement the UART core for FPGA which is located in:
\fpga\cor...
02/14/2017
- JA 09:24 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: FPGA CLOCK LOCATION
- Hello, Good day
Thank you for the answer, I have been working only with the FPGA without using the EMIF interface between the L138 and FPGA.
I want to implement a code done in VHDL and my design contains a clock in its operation l...
02/08/2017
- Hello,
Regarding Table 6 in the datasheet, is this information valid for the commercial or industrial temperature range modules?
Thanks a lot,
Steve
02/02/2017
- AD 12:57 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: CLK2DDR signal on development board
- Hello Franco,
Thanks for checking before committing to the board... The I/O standard does indeed sound like a mismatch!
The likely difference between the 2.5V I/O design building and a failing 3.3V I/O design is due to the (VPD) P... - Hi, I'm designing my own carrier card, but I've some doubts about the use of the bank 4A.
I need to connect the the mitysom module some parallel DACs with 3.3 volts single ended levels as outputs.
I need about 34 pins so I was planning...
01/31/2017
- AB 06:48 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: FPGA CLOCK LOCATION
- Alex,
Thank you for reaching out to us about this question.
On our MitySOM-L138F family modules we have the EMIF bus from the OMAP-L138 connected to the Xilinx Spartan 6 FPGA to allow for communications of cores between the process...
01/30/2017
- Hello good day I developing a new project in ISE WEBPACK using the PROFIBUS DEVELOPMENT KIT with the MitySOM-1810F Processor Card.
I am programming the FPGA and this is my entity:
PORT(
*CLK50* : IN STD_LOGIC;
RX : IN STD_LOG...
01/23/2017
- JA 10:59 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Programming the FPGA - Loading via CPU
- Hello, good day
I load the FPGA with "Example loading the .bin file over the serial port using Kermit" because it was easier but I will continue trying with TFTP server.
U-Boot > loadb 0xC0700000
## Ready for binary (kermit) ... - MW 06:58 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SATA link down
- Are you using SATA-II or SATA-III link speeds? I believe the Errata from TI still applies.
01/22/2017
- FX 10:37 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SATA link down
- hello ,I have the same problem !
Can you tell me this problem is Finish or not?
01/20/2017
- JC 01:51 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Programming the FPGA - Loading via CPU - "ERROR LOADING"
- Jesus Alejandro Alvarez Trejo wrote:
> Hello, Good Day
> ...
Your ping command was run while booted into linux. You should run it while in u-boot to prove you have network communication working.
>
> ...
What tftp server are you usi... - JA 12:51 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Programming the FPGA - Loading via CPU - "ERROR LOADING"
- Hello, Good Day
I am trying to load the FPGA using https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA vía CPU, I already created the .bin file to do the first test. I am using the ...