Mity CPU Platforms

07/25/2024

07:47 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

Hello,
I would look at the avalon memory mapped slave address in your signal tap. It's possible the hps is reques... Gregory Gluszek

07/24/2024

02:31 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

I figure it's about 10% of the CPU when operating 1200 baud and 1 response per second; it gets much lower as you appr... Fred Weiser

07:11 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

Hi,
Yes, I am verified in Signal Tap only. and as off now like, we are able to do read and write HPS to FPGA using... Bhardwaj Kotha

07/23/2024

04:12 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

It looks like you posted a couple different versions of your C code. Which one are you running and what does the outp... Gregory Gluszek

07/22/2024

07:21 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

> before shutting off the 485 driver
Any idea how often the shutting down occurs? Jonathan Cormier

07:19 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

I patched the 8250.c file to increase the 10ms timeout. I found the timeout is really there only to assure the uart t... Fred Weiser

03:16 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

Hi,
In my implementation, the Avalon Memory Mapped interface automatically assigned a base address in platform des... Bhardwaj Kotha

07/19/2024

06:14 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138F Block Diagram Inconsistencies

Dan,
That clears things up perfectly. Thank you for a quick and comprehensive response. Dylan Louviaux

06:10 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138F Block Diagram Inconsistencies

Hi Dylan,
The external input to the Boot Config Block is the EXT_BOOT# signal pin bin 12 of the SO-DIMM connector.... Daniel Vincelette

04:06 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: MityDSP-L138F Block Diagram Inconsistencies

All,
I am designing a carrier board for the MityDSP-L138F with A7 FPGA. I have noticed some inconsistencies with the... Dylan Louviaux

02:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hello,
For the reference project the makefile removes those lines from the sdc file before it does the build, if y... Daniel Vincelette

06:45 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
Yeah, I am removed that two lines in dev_5cs/synthesis/submodules/dev_5cs_hps_0_fpga_interfaces.sdc, before u... Bhardwaj Kotha

07/16/2024

07:40 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hello,
I have verified that the reference design does meet timing when built via the makefile (ie make rbf). The m... Daniel Vincelette

07/15/2024

06:58 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

The most straightforward way to do that would be to create your own Platform Designer Component with an Avalon Memory... Gregory Gluszek

07/13/2024

03:16 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
with the provided reference project there is no packet loss but there are timing errors (screenshots attached)... Bhardwaj Kotha

07/11/2024

01:39 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

It sounds like you are on edge for timing so please verify that your design meets timing via TimeQuest in Quartus. Al... Daniel Vincelette

12:05 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

i had made HPS and emac Splitter Conduit signals to external in Platform Designer and I had assigned that conduit sig... Bhardwaj Kotha

07/10/2024

01:08 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hello,
For the case that you are seeing 60% packet lose, what did you change in the reference FPGA project that wa... Daniel Vincelette

12:07 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

Yes, I wanted to send the 256 BITS of raw data from HPS to FPGA. Can you give me the supplies for that. Bhardwaj Kotha

07/09/2024

05:44 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A module SODIMM pinout documentation error

My mistake. I completely missed the A when I saw this thread. :)
Thanks,
David David Van Sickle

02:43 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A module SODIMM pinout documentation error

Hi David,
The symbol for the MitySOM-AM62 DevKit is for the MitySOM-AM62x and we have verified it is correct. The... Michael Williamson

02:12 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A module SODIMM pinout documentation error

Hello,
This was brought to my attention and I decided to do a quick check of these pins on the AM62 Dev board sche... David Van Sickle

07/08/2024

03:09 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Get URL from jenkins file

I just did a clean pull of the kernel and built it using the poky 3.0.4 sdk with no issues.
It sounds like either th... Tim Iskander

01:20 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: How to access gpio using c code in yocto linux, which is created using PIO IP with HPS

This seems to be a duplicate of https://support.criticallink.com/redmine/boards/45/topics/6705. Please refer to the o... Gregory Gluszek

01:18 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

Hello,
Can you share capture of your console so we can evaluate what commands you are using and exactly what erro... Gregory Gluszek

07/07/2024

01:01 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Get URL from jenkins file

Hi,
I have downloaded the kernel from https://git.criticallink.com/gitweb/?p=linux-socfpga.git;a=shortlog;h=refs... Bhardwaj Kotha

07/05/2024

08:53 AM MitySOM-5CSX Altera Cyclone V Software Development: How to access gpio using c code in yocto linux, which is created using PIO IP with HPS

Hi,
I have added pio ip (output only) to the HPS block design in platform designer, and modified/added gpio block wi... Bhardwaj Kotha

08:51 AM MitySOM-5CSX Altera Cyclone V Software Development: how to access gpio using pio ip core in c code

Hi,
I have added pio ip (output only) to the HPS block design in platform designer, and modified/added gpio block... Bhardwaj Kotha

07/04/2024

07:34 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM

Hi Daniel,
Now am able to generate the boot files.
Thanks & Regards,
Bhardwaj Bhardwaj Kotha

07:02 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
I donot have much resources, as my application need more resources, I wanted to use HPS EMAC. And I am not going... Bhardwaj Kotha

07/03/2024

02:19 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: MityDSP-L138 Power Draw in Deep Sleep? Waking ARM core from DSP core? Power and Sleep Controller (PSC)

Michael Bisbano wrote in message#6697:
> Hi Jonathan,
> Thank you for the response, please let me know what you fi... Jonathan Cormier

01:09 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: oe-layertool-setup.sh script seems to pull and merge when it shouldn't need to

Ok, I did. Nathan Wright

07/02/2024

08:46 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: oe-layertool-setup.sh script seems to pull and merge when it shouldn't need to

I think both of these make a lot of sense. I'd recommend reporting this to TI via the meta-arago mailing list. They... Jonathan Cormier

07:16 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: oe-layertool-setup.sh script seems to pull and merge when it shouldn't need to

while we're at it, why let it complain about detached heads when the config file asked for detached heads?... Nathan Wright

06:51 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: oe-layertool-setup.sh script seems to pull and merge when it shouldn't need to

We noticed in our pipeline setup that the oe-layertool-setup.sh script still appeared to be pulling and merging again... Nathan Wright

07/01/2024

09:16 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: MityDSP-L138 Power Draw in Deep Sleep? Waking ARM core from DSP core? Power and Sleep Controller (PSC)

Hi Jonathan,
Thank you for the response, please let me know what you find out! The system as a whole must be under ... Michael Bisbano

07:05 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: MityDSP-L138 Power Draw in Deep Sleep? Waking ARM core from DSP core? Power and Sleep Controller (PSC)

Michael Bisbano wrote:
> Hi all,
>
> I was wondering if anyone had data on power draw for the MityDSP-L138 in dee... Jonathan Cormier

06:34 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: MityDSP-L138 Power Draw in Deep Sleep? Waking ARM core from DSP core? Power and Sleep Controller (PSC)

Hi all,
I was wondering if anyone had data on power draw for the MityDSP-L138 in deep sleep? My application is bat... Michael Bisbano

06:18 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM

Hello,
You shouldn't need to update the compiler or path from the default that are filled out by the bsp-editor. D... Daniel Vincelette

03:49 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Serial port 2 issue, RS485, RTS drops to early

Fred Weiser wrote in message#6688:
> Changing the timer is probably not in my best interest; my project supports dow... Jonathan Cormier

06/30/2024

05:51 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Get URL from jenkins file

Here is a link to the SDK for the 5CSx
you will need to run it on a linux machine (ubuntu 18 and up recommended)
ht... Tim Iskander

06/29/2024

04:42 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM

Hi Daniel,
Thank you for providing the information regarding booting. I understand the process to boot the... Bhardwaj Kotha

06/28/2024

03:59 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Get URL from jenkins file

If you just need to build the kernel and device tree, you can download the kernel from https://git.criticallink.com/g... Tim Iskander

01:34 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM

Hello,
The Altera Cyclone V SoC boot process involves several steps to initialize and start up the system. The Cyc... Daniel Vincelette