Activity
From 12/13/2011 to 01/11/2012
01/11/2012
- The MityDSP-Pro datasheet states the following:
----"Upon reset the Bank Control Logic defaults to bank zero for boo... - 05:39 PM FPGA Development: RE: Xilinx ISE project file for MityDSP-Pro
- Michael,
I'd prefer to use ISE 13, but I'm fine with 10 or 12 also.
Thanks. - 05:09 PM FPGA Development: RE: Xilinx ISE project file for MityDSP-Pro
- Which version of the ISE are you planning to use?
- Is it possible to get a Xilinx ISE project file for one of the basic MityDSP-Pro builds? If this is on the disk that ...
- 05:24 PM FPGA Development: RE: CE2, CE4, and CE5 addresses
- The FPGA cores stack up on the CE2 address space (0xA0000000). CE3 is reserved for the FLASH memory. CE4 is reserve...
- On the 1.2 GHz C6455 version of the MityDSP-Pro using the XC3S4000, what CE2, CE4, and CE5 EMIF address ranges are al...
- 05:08 PM FPGA Development: RE: Using FPGA cores and library
- Hi Bill,
In short, the hardware\fpga\build_spartan3 folder contains netlists of "cores" (IP functional blocks with... - Do you have a big-picture document describing how to use the multiple FPGA "cores" in the "hardware\boot" folder and/...
- 12:29 PM Software Development: RE: FPGA Interrupts on MityDSP-Pro
- Thanks, that helped.
01/10/2012
- 08:09 AM Software Development: RE: Builds and SYS/BIOS questions ...
- Hi,
In order to actually get the DSP running at 1200 MHz, you will need a macro update to <core/DspMacros.h> to su... - 08:05 AM Software Development: RE: FPGA Interrupts on MityDSP-Pro
- There are 2 lines connected between the FPGA and the DSP intended for interrupt use. On the DSP, 2 GPIO pins are use...
- 07:16 AM Software Development: RE: SYS/BIOS Version 6.x on the MityDSP-Pro
- We have not ported the MDK libraries from DSP/BIOS 5 to SYS/BIOS 6 primarily because the C level code is largely comm...
01/09/2012
- (posted on behalf of a customer)
I am trying to get some documentation on the FPGA/DSP interrupts for the MityDSP-...
01/06/2012
- (posted on behalf of a customer)
I had some early errors regarding -mv64+. I was not aware that the c6455 is a "C6... - (posted on behalf of a customer)
Can I use the new "SYS/BIOS" (version 6.x??) with the c6455? I would like to star...
12/28/2011
- 08:20 AM PCB Development: RE: FPGA/DSP Interface Details & external interrupts
- Doug -
I will let the technical team answer the question about the external interrupts. However, we will add info... - (Posted on behalf of a customer)
I am working on designing the carrier interface board for the MityDSP Pro module....
12/23/2011
- 09:45 AM PCB Development: RE: MityDSP-Pro FPGA questions ...
- > In the directory labeled “C:\MityDSP\2.10\hardware\FPGA_boot” I see several sub directories that appear to have pre...
12/22/2011
- 11:53 AM PCB Development: RE: MityDSP-Pro FPGA questions ...
- (from Anthony)
Michael,
Thanks for the response. From what you describe it seems that the signals I intend to...
12/21/2011
- 07:16 PM PCB Development: RE: MityDSP-Pro FPGA questions ...
- Hi Tom / Anthony,
I hope this doesn't muddy the waters, but here is some more information: There are actually 3 E... - 01:01 PM PCB Development: RE: MityDSP-Pro FPGA questions ...
- ??From the schematics it appears that the evaluation board is connected to both RJ-45 connectors, one goes to the 10/...
- 11:04 AM PCB Development: RE: MityDSP-Pro FPGA questions ...
- Hello Tom,
I will try posting this to the support forum as well but I need to clear up some confusion Kevin and I ...
12/15/2011
- 02:35 PM PCB Development: RE: MityDSP-Pro FPGA questions ...
- The bootloader FPGA image included in the file mention provides a basic UART at pins 14 and 16 of the edge connector ...
12/14/2011
- (posted on behalf of a customer)
RS232_TXD SO-DIMM pin 14
RS232_RXD SO-DIMM pin 16
F...
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