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From 12/14/2011 to 01/12/2012

01/12/2012

04:01 PM FPGA Development: MCS file settings
What file/prom settings should I use when creating an MCS file for my application in the MityDSP-Pro.
-Bob Clarke
Bob Clarke
01:25 PM FPGA Development: RE: Pins used for MityDSP-Pro FPGA bootloader
Mike,
I think you've answered my questions. We're seeing the FPGA ethernet activate on our MDK host board but that m...
Bob Clarke
12:45 PM FPGA Development: RE: Pins used for MityDSP-Pro FPGA bootloader
For other pin usage, you need to consult with the schematic for the host board. The MityDSP-PRO MDK host board schem... Michael Williamson
12:43 PM FPGA Development: RE: Pins used for MityDSP-Pro FPGA bootloader
Are you designing a new board or trying to use the Development Kit board for the PRO?
If you are designing a new b...
Michael Williamson
11:29 AM FPGA Development: Pins used for MityDSP-Pro FPGA bootloader
I'm using the MityDSP-Pro and trying to determine what pins are used by the bootloader so that they don't conflict wi... Bob Clarke

01/11/2012

05:45 PM FPGA Development: Bank switching for different FPGA applications
The MityDSP-Pro datasheet states the following:
----"Upon reset the Bank Control Logic defaults to bank zero for boo...
Bob Clarke
05:39 PM FPGA Development: RE: Xilinx ISE project file for MityDSP-Pro
Michael,
I'd prefer to use ISE 13, but I'm fine with 10 or 12 also.
Thanks.
Bob Clarke
05:09 PM FPGA Development: RE: Xilinx ISE project file for MityDSP-Pro
Which version of the ISE are you planning to use? Michael Williamson
02:25 PM FPGA Development: Xilinx ISE project file for MityDSP-Pro
Is it possible to get a Xilinx ISE project file for one of the basic MityDSP-Pro builds? If this is on the disk that ... Bob Clarke
05:24 PM FPGA Development: RE: CE2, CE4, and CE5 addresses
The FPGA cores stack up on the CE2 address space (0xA0000000). CE3 is reserved for the FLASH memory. CE4 is reserve... Michael Williamson
04:09 PM FPGA Development: CE2, CE4, and CE5 addresses
On the 1.2 GHz C6455 version of the MityDSP-Pro using the XC3S4000, what CE2, CE4, and CE5 EMIF address ranges are al... Bill Dickson
05:08 PM FPGA Development: RE: Using FPGA cores and library
Hi Bill,
In short, the hardware\fpga\build_spartan3 folder contains netlists of "cores" (IP functional blocks with...
Michael Williamson
03:01 PM FPGA Development: Using FPGA cores and library
Do you have a big-picture document describing how to use the multiple FPGA "cores" in the "hardware\boot" folder and/... Bill Dickson
12:29 PM Software Development: RE: FPGA Interrupts on MityDSP-Pro
Thanks, that helped. Bill Dickson

01/10/2012

08:09 AM Software Development: RE: Builds and SYS/BIOS questions ...
Hi,
In order to actually get the DSP running at 1200 MHz, you will need a macro update to <core/DspMacros.h> to su...
Michael Williamson
08:05 AM Software Development: RE: FPGA Interrupts on MityDSP-Pro
There are 2 lines connected between the FPGA and the DSP intended for interrupt use. On the DSP, 2 GPIO pins are use... Michael Williamson
07:16 AM Software Development: RE: SYS/BIOS Version 6.x on the MityDSP-Pro
We have not ported the MDK libraries from DSP/BIOS 5 to SYS/BIOS 6 primarily because the C level code is largely comm... Michael Williamson

01/09/2012

09:49 PM Software Development: FPGA Interrupts on MityDSP-Pro
(posted on behalf of a customer)
I am trying to get some documentation on the FPGA/DSP interrupts for the MityDSP-...
Thomas Catalino

01/06/2012

02:43 PM Software Development: Builds and SYS/BIOS questions ...
(posted on behalf of a customer)
I had some early errors regarding -mv64+. I was not aware that the c6455 is a "C6...
Thomas Catalino
02:42 PM Software Development: SYS/BIOS Version 6.x on the MityDSP-Pro
(posted on behalf of a customer)
Can I use the new "SYS/BIOS" (version 6.x??) with the c6455? I would like to star...
Thomas Catalino

12/28/2011

08:20 AM PCB Development: RE: FPGA/DSP Interface Details & external interrupts
Doug -
I will let the technical team answer the question about the external interrupts. However, we will add info...
Thomas Catalino
08:16 AM PCB Development: FPGA/DSP Interface Details & external interrupts
(Posted on behalf of a customer)
I am working on designing the carrier interface board for the MityDSP Pro module....
Thomas Catalino

12/23/2011

09:45 AM PCB Development: RE: MityDSP-Pro FPGA questions ...
> In the directory labeled “C:\MityDSP\2.10\hardware\FPGA_boot” I see several sub directories that appear to have pre... Michael Williamson

12/22/2011

11:53 AM PCB Development: RE: MityDSP-Pro FPGA questions ...
(from Anthony)
Michael,

Thanks for the response. From what you describe it seems that the signals I intend to...
Thomas Catalino

12/21/2011

07:16 PM PCB Development: RE: MityDSP-Pro FPGA questions ...
Hi Tom / Anthony,
I hope this doesn't muddy the waters, but here is some more information: There are actually 3 E...
Michael Williamson
01:01 PM PCB Development: RE: MityDSP-Pro FPGA questions ...
??From the schematics it appears that the evaluation board is connected to both RJ-45 connectors, one goes to the 10/... Thomas Catalino
11:04 AM PCB Development: RE: MityDSP-Pro FPGA questions ...
Hello Tom,
I will try posting this to the support forum as well but I need to clear up some confusion Kevin and I ...
Anthony Medina

12/15/2011

02:35 PM PCB Development: RE: MityDSP-Pro FPGA questions ...
The bootloader FPGA image included in the file mention provides a basic UART at pins 14 and 16 of the edge connector ... Michael Williamson

12/14/2011

06:13 PM PCB Development: MityDSP-Pro FPGA questions ...
(posted on behalf of a customer)
RS232_TXD SO-DIMM pin 14
RS232_RXD SO-DIMM pin 16

F...
Thomas Catalino
 

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