Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

Michele -

Can I ask for a reminder of what that issue is or a pointer to a forum post? I'm unable to locate it at the moment.

Thanks,
Tom

Hello Tom,
the issue is (or was) on the datasheet of the SOM MityDSP

http://www.mitydsp.com/images/upload/File/MityDSP-L138F%20Spec.pdf

at page 7 you say that :

" The Xilinx 6SLX45 FPGA does not bond I/O Buffers to balls E7, E8, F11,
E11, D12, C12, E12, and F12 of the package used for this module. For
MityDSP-L138F configurations using this FPGA option, these edge connector
signals should be treated as no -connects and will not function as FPGA I/O
lines."

I need to know if the same issue is also on the SOM L138-FG-225-RC using FPGA 6SLX16, or if you solved in the meanwhile.

Thank you very much!

Regards,

MC

Hi Michele,

There is no issue if you are using 6SLX16 FPGAs in any module configuration.

This only a problem with 6SLX45 modules, as the issue is with the wire bonding on the LX45 FPGA chips in the package used by the modules. Critical Link does not intend to alter the design of the MityDSP-L138F SOMs to remove this issue.

If you are using LX16 FPGA SOM option, you are free to use the pins mentioned in your post.

-Mike

Thank you Mike!

Another question: I see that you provide Bank 0 and Bank 1 of the FPGA on the SO-DIMM socket.
Am I free to use, for example, a GPIO Core across the banks, so connecting, for instance, a GPIO pin on a Bank 0 pin and another GPIO pin of the same core on a Bank 1 pin?
Or maybe there is an issue and I must connect all pins of the same core on the same bank?

Thank you very much.

Kind Regards.

Michele

Michele,

In response to your GPIO bank question:

Yes you can use a single core in the FPGA and have it utilize pins from both banks (I have done it in a couple of my designs and have had no issues).

Alex