Activity
From 09/08/2011 to 10/07/2011
10/06/2011
- Hi,
After transferring the jffs2 filesystem via uBoot, using the "nand write.jffs2 C2000000 0 <>" command, is there any method to check whether the file system is fine - before starting kernel - in order to detect block errors or possi...
10/03/2011
- SW 03:48 PM Software Development: RE: uPP digital loopback
- Greg,
I'm using the default ASYNCH3 clock which is PLL_SYSCLK1 I think. This should be divided down automatically. Since I am just using this to test the uPP I won't worry about it and keep the Chan A and Chan B clock divisors equal... - GG 01:49 PM Software Development: RE: uPP digital loopback
- Hi Scott,
As far as I know we have not seen any issue like what you're describing when using a uPP clock driven by the FPGA. Given, we haven't done much work with the uPP in DLB, so it could be a problem unique to that setup.
Anoth... - Hello,
I have a linux driver module to test the uPP in digital loopback. I saw some odd behavior in regards to the clock divisors on Channels A and B. I have the module set to loopback 64 bytes from channel A to channel B. If I se...
09/30/2011
- ME 06:30 AM Software Development: RE: Additional serial port on the MityDSP Profibus dev-kit
- Just thought I'd add a note in case some one else stumbles upon this thread:
Ended up using a Prolific usb-to-serial device that was laying around the office.
I had to build a new kernel with support for usb-to-serial devices and th...
09/29/2011
- Are there test points available on the MityDSP-L138F for the following uPP signals?
'UPP_CHA_ENABLE' = L138 Pin#U16 to FPGA Pin#H5
'UPP_CHA_START' = L138 Pin#W15 to FPGA Pin#C1
'UPP_CHA_CLOCK' = L138 Pin#U17 to FPGA Pin#H7
Than... - SW 10:40 AM Software Development: RE: upp clock
- Greg,
Thanks for the reply. My question was more of how the clocks are setup on the board as a default. I suspected that the clocks were standard with the the uPP xmit clock 300/4 MHz. I found my problem with the uPP code in the en... - ME 08:30 AM Software Development: RE: Additional serial port on the MityDSP Profibus dev-kit
- No, I don't think ssh would work. It has to be something I could open and interact with just like a com port from my code, I'm not sure you can do that with ssh? Either way the recieving end is a windows box and it seems unlikely there w...
- MW 08:18 AM Software Development: RE: Additional serial port on the MityDSP Profibus dev-kit
- (re: comm over ethernet)
Is ssh acceptable? "ssh root@mitydspaddr"
-Mike
- MW 08:17 AM Software Development: RE: Additional serial port on the MityDSP Profibus dev-kit
- The default kernel and root filesystem may "just work". If you plug in the device you should see some messages about it and the device should appear as /dev/ttyUSB0. If that doesn't happen, then you'll need to run make menuconfig and a...
- ME 08:13 AM Software Development: RE: Additional serial port on the MityDSP Profibus dev-kit
- Hmm, I don't really need a physical port. Is there any com over ethernet software availible for these systems?
/ Mattias - ME 08:10 AM Software Development: RE: Additional serial port on the MityDSP Profibus dev-kit
- Thanks for the speedy reply!
One extra port should suffice. I'll order one of the keyspan adapters right away.
I'm using the MityDSP-L138 SoM. Can you point me in the right direction for properly configuring the kernel?
I guess i... - MW 07:49 AM Software Development: RE: Additional serial port on the MityDSP Profibus dev-kit
- Hi Mattias,
I think that your best (or easiest) bet would be to use a usb-to-serial adapter on the Host (USB1) port. If you need more than one, you should be able to use a (powered) hub and attach multiple units. We have used Keyspa... - Hi, I'm wondering what the best way to get an additional serial port is? Is there support for usb-to-serial adapters?
I'm developing something that will need to have both serial, profibus and ethernet support for data transfer and wi...
09/28/2011
- GG 04:35 PM Software Development: RE: upp clock
- Hi Scott,
The fastest you will be able to get the uPP transmit clock to run with your setup is 75 MHz.
From the Upp User's Guide:
"The fixed divisor restricts the maximum speed of the I/O clock to one-fourth the device CPU cloc...
09/27/2011
- I have a userspace upp driver that I am trying to test in loopback mode. I am trying to loopback 1 line of a memory buffer (4096 bytes). I am polling the status register and when it catches the status registers for Q and I appear to ha...
09/23/2011
- We are looking at getting the L138-FI-225-RC that comes with a Spartan 6SLX45. What is the complete FPGA part number that comes on this board?
Thanks,
-Brian
09/21/2011
- SW 05:09 PM Software Development: RE: uPP/DMA registers
- Mike,
I have a couple questions here. I am attempting to write a upp userspace loopback driver/routine. I have memory mapped the pin mux registers, PSC1 registers and the upp registers. I am unsure if the pin mux changes are in eff... - MW 07:51 AM Software Development: RE: Interrupt to ARM side
- Hello Mr. Pailwar,
On the board support package/MDK, in the file sw/ARM/linux/drivers/fpga/fpga_ctrl.c there is some example code of handling interrupts from 2 pins that our framework uses for letting the FPGA interrupt the ARM. We u... - MC 07:29 AM Software Development: RE: HelloWorld dsplink Code composer 5
- Hi Finn
Call me...
/Mads
09/20/2011
- Hello,
I want to generate an interrupt from the FPGA to ARM side of the MityDSP-L138/F board. Is there any example available for doing that and how to make the application aware of the interrupt.
With regards
Pankaj
- MW 10:18 AM FPGA Development: RE: FPGA clock
- On the module itself, the EMA_CLK clock (B7) of the OMAP-L138 is connected to the FPGA. We generally use this clock for most of the core framework we provide. Given the EMIFA must run on this domain, it's convenient and allows us to av...
- Are there any dedicated pins on the FPGA for a clock input? In the IndustrialIO.bin designs do you just use the 100 MHz EMIFA clock as the FPGA input clock? Thanks, Scott
09/19/2011
- MC 05:45 PM Software Development: RE: Mounting USB Flash Memory (mitydspl138)
- Hey Fred,
Yup you were right. After I re-built the kernel with USB Mass Storage support it auto mounted just fine. Thanks for chiming in.
Mike - MC 05:38 PM Software Development: RE: Errors when building custom kernel .config file
- Hi Greg,
From your response I got the sense that this is the sort of thing that should have just worked, so I just tried again & of course it worked. I closed all my shells, opened a new one and went from there. The one hitch was th... - MW 09:04 AM Software Development: RE: HelloWorld dsplink Code composer 5
"sure about CC4 ?? to me, the 'howto' looks like it's made with CCS3.xx....."
It's not. It's CCS4. It's Clearly eclipse based, unless we are looking at different web pages. I am looking at the [[DSP Hello World]] page. I guess ...- FB 08:58 AM Software Development: RE: HelloWorld dsplink Code composer 5
- Hi Mike,
what about unofficial then ?? :-)
sure about CC4 ?? to me, the 'howto' looks like it's made with CCS3.xx.....
maybe somebody else has done this ???
/Finn
- MW 07:16 AM Software Development: RE: HelloWorld dsplink Code composer 5
- Hi Finn,
We have not used CCS5 (officially) here yet.
The Helloworld with DSP link application on our wiki [[DSP Hello World]] was compiled using CCSV4 and several of our developers have migrated to CCSV4 some time ago.
Just wan... - Hi Folks,
Has anybody done the HwlloWorld-dsplink on CCS5 ?? maybe CCS4 ??
best reg
Finn
09/16/2011
- MC 03:01 PM Software Development: RE: Errors when building custom kernel .config file
- Hi Greg,
I cloned a copy from the git repository and I did run the mityomapl138_defconfig command first. I exactly followed the directions in http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Kernel.
After... - GG 02:47 PM Software Development: RE: Errors when building custom kernel .config file
- Hi Mike,
Did you clone a copy of the Kernel from the git repository or are you using what is in the MDK at MDK/sw/ARM/linux/linux-davinci?
Also, did run the 'make ARCH=arm CROSS_COMPILE=arm-angstrom-linux-gnueabi- mityomapl138_defc... - Hi,
I am trying to build a custom kernel that supports USB mass storage according to these isntructions http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Kernel
I was able to build the default image and verif...
09/15/2011
- FW 05:12 PM Software Development: RE: Mounting USB Flash Memory (mitydspl138)
- Hi Mike,
I don't think that is the case; I tried to manually mount as well, but there was no driver in /dev either. Greg sent me a new kernel with USB mass storage support built in, and that worked fine (although I don't recall if it ... - MC 10:33 AM Software Development: RE: Mounting USB Flash Memory (mitydspl138)
- Hi
I am also trying to get a USB disk to mount. Is it possible the USB drive is not auto mounted, but can be mounted manually? What would be the usb device name under /dev?
Thanks,
Mike - MW 11:16 AM Software Development: RE: SATA on MityDSP-L138F dev board
- Glad to hear it!
As for "who is in charge", the filesystem images (our "base" vs. our "full") are basically openembedded images (the "base" console image and an image that includes qt4-embedded libraries with a handful of utilities). ... - MC 10:27 AM Software Development: RE: SATA on MityDSP-L138F dev board
- Hi Mike,
Wow that was easy ;-) It worked right out of the box.
I am curious, who is in charge of the Linux distro that CriticalLink provides?
- SW 10:00 AM Software Development: RE: uPP/DMA registers
- Mike,
I was just planning on mapping the registers and accessing them that way. It looks like there is a specific method for setting the module PSC out of reset, but I assume just writing the correct pin mux value to the register wil... - MW 09:35 AM Software Development: RE: uPP/DMA registers
- Sure you can, though the pinmux setter/getter routines in the kernel are not currently exported.
-Mike
- SW 09:29 AM Software Development: RE: uPP/DMA registers
- Mike,
I see there is nothing in the da850.c file for the uPP, either for clock, or pin muxing. I could just write a kernel module to access the pin mux and PSC registers directly if I don't want to mess with recompiling the whole ker...
09/14/2011
- MW 08:31 PM Software Development: RE: Unable to build root file system
- In theory, you could point it to support.criticallink.com's tree....
Kind of spooky the amount of time git.kernel.org has been down..... hopefully it will be back shortly....
-Mike
- MW 08:28 PM Software Development: RE: uPP/DMA registers
- check arch/arm/mach-davinci/da850.c
There is likely a clock that needs to be defined/enabled for the UPP.
Also there is a power and sleep controller register that may need to be enabled (part of the same clock structures in linux, ... - SW 01:43 PM Software Development: RE: uPP/DMA registers
- Mike,
Where is the clock tree? I think I have printed out the uPP status and control register, and if what I'm looking at is correct it is partially enabled, only the local reset is asserted. Scott - MW 08:23 PM Software Development: RE: Official u-boot with higher baud rate options
- Hi Noman,
I don't see any reason not to support this, but it may take some time for this change to propagate to our factory images/procedures. we'll need to test it here as well, but we'll try to roll it in. Thanks for the feedback.... - Hi,
I would like to get the following change in the next official uboot release. This would allow the use to change the baudrate at the u-Boot and transfer the images at higher baud rate, once the image transfer is complete the baudra... - MW 08:20 PM Software Development: RE: SATA on MityDSP-L138F dev board
- Well Mike,
I think all you need to do is get a powered SATA drive and plug it in. If you are using our provided filesystem (well, really just udev) and the default kernel you should have SATA support. The config option should be:
... - Hi,
I am looking to get some relatively quick proof of concept & testing of the SATA functionality with the MityDSP-L138F module and dev board.
Could you possibly point me to some resources on how to get a SATA drive running with e... - GG 10:52 AM FPGA Development: RE: ucf file
- Hi Scott,
Yes, you should be able to use the same UCF file. The pin mapping between the LX45 and LX16 is the same, the only issue is that there are 7 or 8 pins on the LX16 that are not connected on the LX45. If you try to use these pi... - We have a MityDSP L138 development kit with the Spartan 6 LX16 FPGA. We are in the process of purchasing the MityDSP L138 with the Spartan 6 LX45 PFGAs. Do we use the same ucf file for both fpga's found in the MDK release? That would ...
09/13/2011
- NS 09:59 AM Software Development: RE: Unable to build root file system
- Hi Mike,
build-essential is now installed. However, i realized that the checkout was not done because it was not in the right directory. I corrected the steps as below:
#bash> export MDK=/home/mitydsp/MDK_2011-03-31
#bash> cd ${MD... - MW 07:31 AM Software Development: RE: Unable to build root file system
- Hi Norman,
A couple of observations:
1) The package name is "build-essential" not "build-essentials", I will try to correct the original wiki page. Sorry about that.
2) When you cloned the openembedded setup, did you check out... - MW 07:25 AM Software Development: RE: ymodem
- Hello Mr. Nagel,
We've never tried using ymodem here at Critical Link as serial download speed hasn't been an issue. Folks generally have a faster interface to the device or do it during kernel runtime, or use kermit, which we haven'...
09/12/2011
- Hi,
What is a better option to upload a file (uImage for example) at U-boot prompt ?
When ymodem transfer fails, u-boot stays in loop forever, unable to interrupt.
kermit seems slower than ymodem.
Are there any known problems usin... - Hi Mike,
I was trying to build the root file system using the instructions on the wiki but getting lot of errors. Could you please take a look at the attached file and let me know if i am missing something.
Thanks,
Noman
09/09/2011
- GG 04:45 PM Software Development: RE: IndustrialLO.bin
- Hi Scott,
Yes, the IndustrialIO.bin file distributed in the MDK has the base module and other cores built in and you can access them through the EMIF interface.
The cores in IndustrialIO.bin are:
constant CORE_BASE_MODULE : inte... - Hello,
I am working with writing drivers to access FPGA registers on the EMIFA. I currently don't have any custom vhdl code. My end design will have me access some dual port ram on the FPGA via CS3 on the ARM. Until I get our desig...
09/08/2011
- TC 04:29 PM Software Development: RE: no serial data when first using dev kit
- Mike -
Glad you are up and running. Good point about the out of box experience.
Thanks,
Tom - MC 04:25 PM Software Development: RE: no serial data when first using dev kit
- Hi Greg,
That was it! I did not use the cable supplied because I always have serial cables connected to my computer.
On that note, the DVD should really have a simple getting started pdf explaining things such as the null modem ca... - GG 04:20 PM Software Development: RE: no serial data when first using dev kit
- Hi Mike,
J502 is the default RS232 port and the ribbon cable is meant to be used on this port for RS232 communication.
My guess is that you are not using a Null Modem cable and that is the reason you see nothing over RS232. Let us ... - Hi,
I am just starting to get my Dev kit up and running with the L138f Module. I am used to the Embedded Linux dev environment, and was under the impression that I should be able to get a Bootloader running right out of the box over...