Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

06/02/2017

12:14 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX

The QSPI NOR is supported by the MTD layer, so you should be able to partition it and mount it using JFFS2 (or perhap... Michael Williamson

12:05 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX

We're using the 5CSX-H6-4YA so we should have 32MB of QSPI NOR, and we are booting from SD card, though it's possible... Stephen Snyder

10:25 AM Software Development: RE: Using EEPROM available on MitySOM-5CSX

Hi Jared,
If you are looking for a small amount of space, there is also some memory available in the RTC. There i... Adam Dziedzic

06/01/2017

11:52 PM Software Development: RE: Using EEPROM available on MitySOM-5CSX

Hi Jared,
Before you get into the I2C EEPROM, does the MitySOM you are using have the QSPI NOR FLASH installed (mo... Michael Williamson

10:39 PM Software Development: Using EEPROM available on MitySOM-5CSX

+Context:+
My team would like to store some non-volatile data specific to a unit of hardware (independent of the S... Jared Kirschner

05/23/2017

08:32 PM Software Development: RE: Altera spi

Brian,
Glad to hear it! You're welcome
Dan Daniel Vincelette

06:24 PM Software Development: RE: Altera spi

Dan,
Got it working. Thanks for all the help.
Brian Brian Wentworth

06:12 PM Software Development: RE: Altera spi

Brian,
It looks like the Altera GPIO documentation is wrong, in the the driver it's looking for GPIO interrupts to... Daniel Vincelette

05:57 PM Software Development: RE: Altera spi

Dan,
I just tried this and I'm getting the same error. I posted my updated dts.
Thanks,
Brian Brian Wentworth

05:55 PM Software Development: RE: Altera spi

Dan,
I just tried this and I'm getting the same error. I posted my updated dts.
Thanks,
Brian Brian Wentworth

05:28 PM Software Development: RE: Altera spi

Brian,
I think this variable was changed to "altr,interrupt-trigger" in the newer kernel. Here is the documentatio... Daniel Vincelette

05:23 PM Software Development: RE: Altera spi

Dan,
I have most of it working. The only problem I see now is the gpio not showing up. I'm getting the following err... Brian Wentworth

02:38 PM Software Development: RE: Altera spi

Brian,
Can you post your boot output?
I would recommend doing a diff of the DE0 nano board dts and that one. Th... Daniel Vincelette

08:21 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case

Glad to hear you got it to work!
Dan Daniel Vincelette

06:48 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case

Dan,
solved also this step!
I rebuilt the my kernel version using the default .config you suggested me, modified... Gianni Casonato

05:20 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case

Glad to hear!
I used our mitysom5csx_devkit_defconfig that is part of our 3.16 kernel
kernel: https://support.c... Daniel Vincelette

05:04 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case

Dan,
thanks for it.
I've added the spi0 section at the bottom of my dts and it works!!! Fantastic!!
The only po... Gianni Casonato

02:32 PM Software Development: RE: Virtual SPI device setup and access using spidev - Altera Cyclone V case

Hello Gianni,
I see that you've tried to add both the spidev devices to a FPGA spi core and the HPS peripheral. I ... Daniel Vincelette

05/22/2017

07:59 PM Software Development: RE: Altera spi

Dan,
I compiled the rel_socfpga-4.1.33-ltsi-rt_17.05.01_pr branch of the kernel form altera open source. I replaced ... Brian Wentworth

05/20/2017

08:01 AM Software Development: Virtual SPI device setup and access using spidev - Altera Cyclone V case

Ref: <similar message in ARM9 Based Platforms Forum> https://support.criticallink.com/redmine/boards/10/topics/5285
... Gianni Casonato

05/19/2017

05:41 PM Software Development: RE: Altera spi

Brian,
Trying to avoid a board spin is fully understandable. Yes, you should be able to use that kernel on the mit... Daniel Vincelette

05:20 PM Software Development: RE: Altera spi

Dan,
I got the Altera spi working on a DE0 nano board with the latest rt kernel form altera : rel_socfpga-4.1.33-l... Brian Wentworth

03:47 PM Software Development: RE: Altera spi

Brian,
I'm sorry for the delay. I've been able to recreate your issue and after looking around Altera's spi kernel... Daniel Vincelette

05/15/2017

12:23 PM Software Development: RE: Altera spi

Dan,
Sorry for the delay. I've been out of town. Here is the c file that I was using to test the spi.
Thanks,
Brian Brian Wentworth

05/10/2017

03:27 PM Software Development: RE: Altera spi

Brian,
Would you mind posting your updated spi_test.c? I'll see if I can recreate what you're seeing on my dev kit... Daniel Vincelette

05/09/2017

06:46 PM Software Development: RE: Altera spi

Thanks Dan,
This cleared up the errors on the DTB. I have tried to run the spi_test.c provided in a different post a... Brian Wentworth

05/08/2017

06:18 PM Software Development: RE: Altera spi

Hi Brian,
Sorry you'll also have to set #size-cells to 0x0 for the altera spi driver nodes, this info was taken fr... Daniel Vincelette

05:11 PM Software Development: RE: Altera spi

I'm still getting the same error. Brian Wentworth

04:57 PM Software Development: RE: Altera spi

Hi Brain,
Sorry for the delay. Looking at the warnings you're getting from the critical link toolchain you need to... Daniel Vincelette

01:24 PM Software Development: RE: Altera spi

I was able to comply the DTB using a tool chain from rocketboards and a spi device showed up under /dev/spidev. Writi... Brian Wentworth