Automatic SOM Power On Circuit¶

The Qualcomm SOM differs from other Critical Link SOMs in that after power is applied, it requires a pulse on the POW-BTNn signal to power up the SOM. As this isn't ideal for every application, Critical Link has designed and verified an automatic power on circuit. This circuit uses the Texas Instruments TPL5111 nanoTimer. This is a low-power system timer designed for power gating battery-powered applications.

Configuration¶

The TPL5111 is powered from the same 3V7-BAT rail that supplies the SOM. This way, when power is applied to the SOM, the TPL5111 will start its operation. A 0.1uF capacitor is used at the VDD pin of the device as per the datasheet's recommendation.
For the DELAY pin, a 4.99kΩ resistor is used which results in a pulse width of ~950ms. The MitySOM-QC requires a pulse width of at least 400ms and a pulse longer than 10s results in a reset. Approximately 1 second was targeted to give ample headroom from the 400ms while still being responsive to the power being applied. Smaller pulses could be used but should be investigated with the specific hardware to ensure that hardware/device variability still results in at least 400ms pulses.
The DRVn pin is the output of the TPL5111. As the device is powered from 3V7-BAT, this signal should be connected to the gate of an NMOS FET to result in an open-drain drive on the POW-BTNn pin. If required, a button can still be connected in parallel to the NMOS FET so that the device can be reset by the user.
The DONE pin is pulled to ground in both cases as that signal is used to cut the pulse short which isn't necessary in either mode.
The EN/ONE_SHOTn pin is the main pin that differentiates the two modes.

Modes¶

The TPL5111 can be configured in two modes:

One Shot Mode¶

In One Shot Mode, after power is applied to the timer, it produces a single pulse. To accomplish this, EN/ONE_SHOTn should be connected to GND. The schematic is shown below. This is a snippet of the MitySOM-QC Dev Kit with the addition of the TPL5111.
Note that if the SOM powers down for any reason then the TPL5111 will NOT turn the SOM back on until the voltage on 3V7-BAT is removed and re-applied.

Timer Mode¶

In Timer Mode, after power is applied to the timer, it will continue to produce pulses on DRVn at regular intervals until the EN/ONE_SHOTn signal is pulled low by the SOM, indicating successful boot. To accomplish this, EN/ONE_SHOTn should be connected to VDD through a pull up resistor and connected to ground with an NMOS FET. The gate of the FET should be connected to either a GPIO or 1V8-SOM so that when the SOM is booted, the TPL5111 is disabled.
Note that if the SOM powers down for any reason then the TPL5111 will re-enable turning the SOM back on as long as as voltage is present on 3V7-BAT.