Activity
From 11/07/2013 to 12/06/2013
12/06/2013
- DV 03:14 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HSMC to GPIO
- Hi Jack,
The 5CSX dev board follows the Altera defined pinout for HSMC so that should work.
Dan -
03:00 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: HSMC to GPIO
- Hi,
Is HSMC on base board laid out the same pin out as this particular Terasic daughter board (this is what Altera follows in their layout)
I attached the manual for the daughterboard.
Thanks!
Jack - MF 11:49 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- I don't see a SPI /dev/ entry.
Tried this (as in the example at https://www.kernel.org/doc/Documentation/spi/spidev_test.c) - GG 11:07 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- Hi Mary,
Reading and writing over a SPI bus on Linux is pretty simple. You need to open a file descriptor for the SPI /dev/ entry and use ioctl SPI_IOC_MESSAGE commands to send spi_ioc_transfer structs to the device.
Here's a for... - How do you read/write to a device on the SPI1 bus (CS1) on the ARM side? Is there an example? Can I do low level register read/writes or is there a driver?
I am using MDK_2012-08-10
I have recompiled the kernel with a custom base... - JC 09:43 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Once you have the network connection up you can easily move files using ssh and winscp.
- JC 09:39 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- It maybe of use to you to have the usb port act as a network device so you can send files over the network. See http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Enabling_USB_RNDIS_Support.
- I have inherited development responsibility for a custom base board using an OMAP-L138F SoM. I need to get USB working in one manner or another.
The cable designed by the board originator has a USB-A type plug on it, implying that ...
12/05/2013
-
06:14 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Beautiful Work! Thank you so much!
Jack -
05:57 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- O of course! Can't believe something simple like that slipped my mind.
Thank you so much! Hope this works!
Jack - DV 05:51 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Jack,
1) Hmm, I believe that error is from qsys generate not being run. Let me know if after running generate if that error still comes up.
2) Yes that is correct, it just needs follow the "Avalon Stream Standard":http://www.alt... -
05:35 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
A couple of issues:
1. I am having trouble compiling the code. It's returning warnings and errors like such:
Warning (125092): Tcl Script File mityarm_5csx_dev_board/synthesis/mityarm_5csx_dev_board.qip not found
Error ... - DV 03:34 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Jack,
I have created a new wiki section and have added the hps ddr example there. "LINK":http://redmine.criticallink.com/redmine/projects/mityarm-5cs/wiki/Writing_to_HPS_Memory
Dan - SH 02:59 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP software sometimes does not start
- Thanks for the reply Mike - I took a look at my code and the Debug outbound is created before the inbound in the DSP software. In any case, the problem "went away" - after a couple of glitches after first loading the software in the /mn...
- MW 12:37 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP software sometimes does not start
- I suspect that you may have a race condition between the ARM and the DSP setting up inbound and outbound message Qs.
The inbound message queues create local message q structures. The outbound message queues attempt to continuously a...
12/04/2013
- DV 08:23 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hey Jack,
My plan is to get it up Thursday afternoon. I currently have the FPGA side done but need to finish up the linux side and test it.
Dan -
05:18 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Dan,
When would you be able to make the examples available?
Thanks!
Jack - I have a strange problem with starting up some software on bootup. I have followed the instructions in this link:
[[http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/ARM_Software_FAQs]]
with a line that looks like... - GG 01:46 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Loading DSP-Code from Linux without DSPLink/DSPBios
- Hello Benedikt,
As far as I know, we've really only had experience running DSP code that uses the BIOS. Have you downloaded and looked at our MDK or our [[DSP Hello World]] starter guide? In the MDK we have a class called dspapp that... - Hej hej,
I have a coff-file with my DSP-Algorithm which runs perfectly when I start it via JTAG or via U-Boot. [Linux is up on the ARM in parallel. The communication between Linux and DSP is also working.]
Now I want to load the DS...
12/03/2013
- JC 04:21 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Read-only file system using systemd for startup
- I think that's the first step. The programs that have problems should then print error messages in the boot log. Might make things easier to take a boot log of the rw and ro boots to compare them so you can find the errors easier.
- SH 04:19 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Read-only file system using systemd for startup
- Yes, I was going to try just updating /etc/fstab and the bootarg environment variable and see if that works...what do you think?
- BD 02:48 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Read-only file system using systemd for startup
- Stephen,
Do you have an /etc/fstab in your filesystem? Have you tried updating that file as described in step 4?
-Bob
12/02/2013
- There is a discussion of how to set up a read-only filesystem in the following link:
[http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Configuring_a_Linux_Filesystem_for_Uncontrolled_Shutdowns]
but the instruction... -
04:28 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Dan,
We would like to use the HPS DDR as well, but as you can see from my numerous posts, we are really stuck on memory write to multiple addresses. So while you guys are preparing an example for writing to the HPS DDR, we will hav... - DV 04:17 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Jack,
Hmm, are you using the DDR SDRAM Controller with UniPHY in your QSYS project?
Also with this first release of the 5CSX SOM there is a special hardware modification that is needed in order to get the FPGA DDR to work, which... -
02:34 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Dan,
I don't see the TCL file that you are referring to. All the tcl files that I have are for HPS DDR not FPGA except for the one that you attached.
I attached the a print screen showing all the files.
Jack - DV 02:30 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Jack,
Did you also run the IO Standard TCL file generated by the tools?
Dan -
02:25 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Dan,
I ran the tcl script that you attached on this thread.
But when I tried to compile, it gives me errors like the following:
Error (169026): Pin FPGA_DDR_A[0] is incompatible with I/O bank 5A. It uses I/O standard 2.5 V, w... - DV 02:21 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Jack,
The IO Standard TCL file should be auto-generated by the tools.
To run it from Quartus:
1) Go to Tools->TCL Scripts
2) In the TCL Scripts window you should see multiple tcl scripts, there should be one that looks like mi... -
12:32 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Dan,
Could you provide the TCL file for the IO Standard as well please?
Thanks!
Jack - DV 10:52 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Jack,
I have attached a TCL file that will setup the pin assignments for the FPGA DDR.
Dan -
11:31 AM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: Link Down
- Hi Dan,
It happens while it's idling and booting up.
Thanks!
Jack - DV 11:05 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Link Down
- Hi Jack,
Is this while the dev kit is just idling in linux? Or is this just during boot up?
Dan - DV 11:03 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Jack,
Have you taken the SDRAM FPGA port out of reset? The register is called hps.sdr.ctrlgrp.fpgaportrst, the description can be found in "HPS Addressmap":http://www.altera.com/literature/hb/cyclone-v/hps.html#hps.sdr.ctrlgrp.fpga... - MW 10:44 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: problem with spinlocks in linux kernel module
- Steven,
I think the reason why you see the difference is that your PC is likely a multi-core (multi-processor), on single core systems spin_lock and spin_unlock really don't do much for you because that is the only possible thread run... - Hi,
I tried to run a trivial test driver pasted in below on a PC using Redhat linux and on the ARM core of the OMAP-138 using Angstrom linux. The function "spinlock_test" trys to obtain a spinlock it has already by calling itself two ... - NK 12:51 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Regarding developing real time application"
- Hi Mike,
We are planning UART from linux on arm9 cortex. Or can you suggest any feasible solution in this regard, as we are planning DSP only for image algorithms.
With regards,
Naveen K S
11/30/2013
- MW 07:34 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Regarding developing real time application"
- Do you mean using a "UART from Linux":http://en.wikibooks.org/wiki/Serial_Programming/Serial_Linux? Or are you trying to use the UART with the DSP?
I'm afraid we can't help you design your application without detailed requirements.
... - Dear sir,
we are working on developing vision system, wherein we are using your mitydsp L138F SOM and Industrial I/o Board (as a sub system module in our entire system) for image processing. Our requirement is we need to interact with... - MW 07:29 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Driving DVI-D with Spartan6 LX45 Fpga
- The issue cannot be resolved without redesigning the PCB.
If you are using an LX-45, you cannot use the DVI interface on the dev kit. Why Xilinx did not bond out these pins remains a mystery.
I am sorry for any inconvenience.
... - From the following discussion, it is said that Spartan6 LX45 FPGA based MityDSP-L138F SOM cannot drive DVI-D on Industrial IO boards. Is this case true now also or this issue resolved??
Kindly reply as soon as possible.
Thanks in Adv...
11/28/2013
-
04:57 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: FPG DDR3 Memory Pin Assignment
- Hi,
Can you please provide the pin assignment for the optional FPGA DDR3 memory please?
Thanks!
Jack - MW 07:52 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Regarding driving two displays using MitydspL138F vision development kit"
- The DVI interface on the L138F / Industrial I/O kit is DVI-D (see "wikipedia page about DVI interface types":http://en.wikipedia.org/wiki/Digital_Visual_Interface) compliant only.
To drive the displays you have attached using the VGA ... - "
ARM9 Based Platforms - Software Development: RE: "Regarding Driving Displays in MitydspL138F Vision Devlopement Kit"
Michael Williamson
If both the LCD display and the display connected to the DVI interface can run using the timin...
11/27/2013
- MW 08:09 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Regarding Driving Displays in MitydspL138F Vision Devlopement Kit"
- If both the LCD display and the display connected to the DVI interface can run using the timings (e.g., same resolution, same pixel clock rate, same front / back porch settings, same vertical refresh rate) then you should be able to run ...
- Hi sir,
Initially our requirement is to drive two displays in MitydspL138F VDK.
In Mitydsp L138F based vision development kit datasheets it was given LCD panel interface and DVI interface are provided. Can we drive two displays bot... -
05:07 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- I read through the section for the Cyclone V on the HPS-FPGA AXI and the manual for the SDRAM that we are using but I can't find any info so I would appreciate your help.
I can get data stored in one location of the memory. But when I...
11/26/2013
-
04:37 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi,
Can someone please get back to me on this?
Thanks!
Jack
11/23/2013
- MW 03:34 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: JFFS2 driver errors
- You can do it in the DSP using tcDspSyscfg::SetMasterPriority() in the dsp core library.
-Mike
- SH 01:30 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: JFFS2 driver errors
- Thanks for those suggestions, Mike. According to Table 11-2, the default priority for EDMA is 0 (highest) and for ARM instruction and data is 2 (lower). When I look at these registers in debug mode (DSP), I see these default priorities...
- MW 08:40 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: JFFS2 driver errors
- Hi Steven,
Is the DMA priority configured higher than the ARM data access priority in the Master Priority Configuration registers (see the OMAP-L138 Technical Reference Manual regarding DMA bus mastering priority)?
We have seen FPG...
11/22/2013
- I'm seeing some errors similar to those mentioned in the following thread:
http://support.criticallink.com/redmine/boards/12/topics/2954
I am using the CL FPGA modules for EMIF, etc with no changes and making DMA transfers from the FP... - GG 05:01 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Quartus II Subscription Edition Error
- Hi Jack,
Perhaps the project was corrupted when you upgraded it to the 13.1 tools. I've attached a copy of the project that has been successfully upgraded to build in the 13.1 tools.
Let us know if you have any issues.
Thanks... -
03:29 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: HPS Memory Controller
- Hi Mike,
Can you provide for me the exact product number for the Micron SDRAM on board. I need information on the timing parameters for those memories.
Thanks!
Jack
11/21/2013
-
02:10 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: Quartus II Subscription Edition Error
- Hi Greg,
I am using 13.1 Quartus, and I ran the script that you recommended and the error that I sent you was what I got after I ran the script. So it's not from the compiling part, but just the script.
Thanks!
Jack - GG 02:08 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Quartus II Subscription Edition Error
- Hi Jack,
Are those the same errors you were receiving before? And typically when Quartus reports an error there is a plus symbol next to it that you can use to expand the error message and get more details. Could you provide us with ... -
12:35 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: RE: Quartus II Subscription Edition Error
- I tried running the tcl script and it didn't work.
The errors are:
Error: Quartus II 64-Bit TimeQuest Timing Analyzer was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 368 megabytes
- GG 09:02 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Quartus II Subscription Edition Error
- Hi Jack,
What version of the Quartus tools are you using?
That project was built with the 13.0 sp1 tools. If you've updated it to the 13.1 tools you probably need to run the hps_sdram_p0_pin_assignments.tcl. Select Tools -> Tcl Sc... - MW 07:14 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Compiling the HelloWorld application with CGT
- You should dump out the full build texts between the two operations and compare.
I suspect that the memory configuration templates (which define the shared regions for DSPLINK) are somehow not the same between the 2 builds.
-Mike
- MW 07:05 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- HI Jack,
I suggest you head over to the "Cyclone V Documentation page":http://www.altera.com/literature/lit-cyclone-v.jsp Altera web site for this information.
The documentation is extensive, and should provide the information you ...
11/20/2013
-
06:25 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: HPS Memory Controller
- Hi,
Could you guys provide some documents and timing diagrams for the HPS memory controller?
Thanks!
Jack -
04:53 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: Link Down
- Hi again,
I have the ethernet connected to the development kit, but on the console it kept on giving me the following"
libphy: stmmac-0:03 - Link is Up - 1000/Full
libphy: stmmac-0:03 - Link is Dowwn
Repeated for a few seconds. B... -
03:51 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: Quartus II Subscription Edition Error
- Hi,
I am using the mityarm_5csx_dev_board project that you guys have. If I use the web edition of quartus to run it, everything is fine, but if I use the subscription edition of quartus ii I get some errors.
First of all, when I op...
11/19/2013
-
05:49 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: Ethernet
- Hi,
How can I configure the FPGA such that the ethernet will still be functioning after I program it. I notice that the ethernet is down after I load the fpga.
Cheers,
Jac - MW 05:25 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Clock
- There is a 25 Mhz clock brought in on the main HPS_CLK1 input (pin E20). It's actually defined in the Qsys HPS component of the reference project. Qsys automatically connects the HPS clocks during the build process. You can route this...
-
05:18 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: Clock
- Hi,
Where is the clock on the MityArm?
I am using your mityarm_5csx_dev_board project, and it's not there. Could you provide me the pin assignment for your clock please?
Thanks!
Jack
11/18/2013
- Hi,
I was trying to compile the DSP HelloWorld Application available at the following location. http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Hello_World. I got both the ARM side and the DSP side files to co... - MW 05:04 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Unable to access Linux
- Hi Jack,
We haven't trying using an Altera MMK, we instead us the USB Blaster or the USB Blaster II directly. Is it possible that the Altera MMK is holding the reset pin active?
You can load the FPGA via an Raw Binary File without... -
04:38 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: Unable to access Linux
- Hi,
I am having trouble accessing the Linux system on the SD card, when the MityARM is connected to the PC, meaning that I can't access on putty. However, when it's not connected to the PC via the programmer board (Altera MMK), I can ... - MW 05:01 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Input/Output interfacing
- Hi Rich,
You need to be careful with the pin assignments. If you change an assignment that is by default controlled by the HPS subsystem to FPGA fabric (or vice-versa) you will need to regenerate the Altera "Pre-Loader" (first stage ... - MW 04:57 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA - HPS DDR Memory
- Hi Jack,
I would recommend using Qsys and exporting the FPGA->HPS DDRAM bridges. Then if you create an Avalon memory mapped controller (spec including the timing diagrams can be found "here":http://www.altera.com/literature/manual/mn... -
04:42 PM
MitySOM-5CSX Altera Cyclone V
FPGA Development: FPGA - HPS DDR Memory
- Hi,
I need to design system where I store input data to the memory via the FPGA, and then export it out to my computer through the HPS.
My only problem is that I am not very familiar with using the AXI bridge. Can someone please pr... - BK 11:58 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: EDMA conflict DSP <-> Linux
- Hej Mike,
I just checked the master priorities. I changed it to the following values:
> 0: EDMA3_0_TC0
> ...
I use EDMA3_0_TC0 for the McASP-transfers and EDMA3_0_TC1 for all other requests.
Unfortunatly the behavior is exactly t... - MW 10:42 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: EDMA conflict DSP <-> Linux
- The reservation of resource may be non-sense, but the resources specific to device drivers (like McASP channel queues) will not be touched by the linux kernel if the drivers are not activated, so I suspect that is not the problem.
Ins... - BK 09:54 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: EDMA conflict DSP <-> Linux
- The bug was in the param-sets of the edma which were not set correctly in my application.
But now I have another issue with the edma:
I use linux on the ARM to configure external devices via I2C like DAC/ADCs and to communicate via... - BD 10:06 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linux startup with app running after boot
- Steven,
Once you have your program output going to stdout, you can redirect it to a file that can be viewed after the system boots: - JC 09:31 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linux startup with app running after boot
- You should be using normal stdout printf's in your program and not opening the serial port.
11/16/2013
- SH 08:13 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linux startup with app running after boot
- I was wrong about starting the app with the full pathnames for both the app and the DSP executable. I wrote a service to start it up that way, and it works, but it crashes the terminal program (I am using Putty) and I have to restart my...
11/15/2013
- SH 07:26 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linux startup with app running after boot
- Thanks for that, but how do you do the same thing with a systemd service? My filesystem is using systemd for startup.
- TI 06:30 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linux startup with app running after boot
- Steven
In your script that runs the app, just "cd" to the correct directory. I.e.
cd /mnt/user_nand
./myApp mydspExecutable &
cheers
/Tim - SH 06:27 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linux startup with app running after boot
- I have what might seem like a dumb question. I like the idea of starting the app as a service, and I have written and tested a service that loads the fpga_ctrl and DSPLink modules on startup. My application and the files it needs to ru...
11/14/2013
- JJ 03:40 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM-335x Development Kit touch screen
- Thanks Jonathan.
I just pulled down the latest from the mityarm-linux-v3.2 branch and the touchscreen is working. - JC 01:22 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM-335x Development Kit touch screen
- Jesse,
I just pushed an update to the 3.2 branch.
Upon further investigation it was found that the 3.2 change included some behind the scenes changes to how ti was initializing the touchscreen. A new omap_hwmod interface was added ... - RB 02:39 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Input/Output interfacing
- Thanks Mike,
I was able to export the signals I wanted and they now show up in Pin Planner.
Is it in general ok to retask signals in the 5CSX_IO class?
For example, I see that on Module Pin Number 60 corresponding to CYCLONE pin AH2...
11/13/2013
- MW 01:41 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Input/Output interfacing
- The FPGA ball numbers can be mapped to the edge connector via Table 7 in the "datasheet":http://www.mitydsp.com/images/upload/File/MityARM-5CSX-Datasheet.pdf.
The devkit baseboard schematic is "here":http://support.criticallink.com/re... - JC 10:35 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM-335x Development Kit touch screen
- Jesse,
I agree that doesn't look like it would be the problem.
11/12/2013
- RB 07:03 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Input/Output interfacing
- Also, I don't know if I have seen a file which shows which physical pins on the FPGA end up on which physical connectors/pins on the carrier board.
Can you point me in the right direction?
Thanks! - RB 07:01 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Input/Output interfacing
- Hi Dan
Yes, I have done exactly as you described.
I haven't worked with the Pin Planner as of yet, so I'll take a look at that tomorrow.
So if I understand correctly, after I do a successfule Analysis and Synthesis step, the signals... - DV 05:49 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Input/Output interfacing
- Hi Richard,
I'm guessing you've created a component with a conduit for these external signals and you've exported this conduit through qsys to your top level entity, is this assumption correct? If it is then you can use the pin planne... - I have built a custom component in QSYS as a memory-mapped avalon slave and been able to interface it
correctly so that I can communicate with it via the ARM processor as expected. This module also provides
some I/O signals that I want... - JJ 06:20 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM-335x Development Kit touch screen
- When I diff the config file between the two branches ( git difftool mityarm-linux-v3.2 AM335XPSP_04.06.00.02 -- arch/arm/configs/mityarm-335x-devkit_defconfig ), I don't see any changes to CONFIG_TOUCHSCREEN_TI_ADC or CONFIG_TOUCHSCREEN_...
- JC 05:45 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM-335x Development Kit touch screen
- Jesse,
It also looks like when we switched from 3.1 to 3.2, we switched from the touchscreen driver we wrote to the one that TI added in 3.2. If you could switch back to ours and report whether it starts working that would be a good f... - JC 05:24 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM-335x Development Kit touch screen
- Jesse,
This is a known issue with the current 3.2 kernel. Noted here: http://support.criticallink.com/redmine/projects/armc8-platforms/wiki/Cl_v32_AM335XPSP_#Known-Issues
I was unable to determine why the touch events were coming i... - I am having trouble using the touch screen on the MityARM-335x Development Kit wit the mityarm-linux-v3.2 branch of the kernel repository.
I built the boot loader using instructions from : http://support.criticallink.com/redmine/pro... - JC 02:33 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: EDMA conflict DSP <-> Linux
- Was the bug in the kernel or your application?
- BK 02:09 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: EDMA conflict DSP <-> Linux
- Found the reason. The DMA configuration was wrong.
- TI 07:59 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linux startup with app running after boot
- Steven
One other note..
If you are using a newer filesystem with systemd (does /etc/systemd exist) things are a bit different. The link in step 4 talks about it a bit.
cheers
/Tim - TI 07:52 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linux startup with app running after boot
- Steven
1 - No you don't need to log in as root... the init system will run your script for you. One thing that may catch you (it got me) is that HOME will not be defined when your script is run by init.
2 - Copy a simple script in /e...
11/11/2013
- I am at the final stage in getting my project working on the MityDSP L138 board. I want to load the FPGA control module and the DSPLink module and then start my application, which is designed to run until the sun goes nova or the batter...
11/09/2013
- BK 06:06 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: EDMA conflict DSP <-> Linux
- Hej Mike,
I'm using my own board and also my own baseboard-configuration.c which is based on your baseboard-industrialio.c. I removed everything related to SPI, McASP and USB - espacially the functions
> baseboard_setup_spi();
> ......
11/08/2013
- MW 01:56 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: EDMA conflict DSP <-> Linux
- What baseboard file are you using?
The devkit one configures MCASP for use by the ARM/linux. Could be a resource contention?
The board-da850-evm.c code is reserving EDMA channels such that the linux OS doesn't try to use them. ... - Hej,
I try to use the EDMA to copy data from the McASP to and from a buffer for further processing on the DSP.
If I don't use the EDMA but McASP interrupts to copy the data it works fine, but when I try to use the EDMA it does not ...