Customizing the On Board Silicon Labs PLLs¶

(this is a work in progress)

Creating a custom PLL binary configuration file¶

Download the Silicon Labs Clock Builder Software¶

The Silison Labs clock builder software must be used to configure the PLL settings for the SI5338 clock chips. The software can be downloaded from Silicon Labs Clock Builder Pro website.

Determine Which PLL (U14 or U15) you need to customize¶

Launch the Clock Builder Application¶

Select the Clock Generators Application¶

Select the Si5338 Chip¶

Configure the Pin 3 / Pin 4 to use the IN3 (CLKIN) and I2C_LSB option¶

Set the Device Address and I2C Voltage Level¶

For U14, the I2C address must be set to 0x71. For U15 the I2C address must be set to 0x70.

The I2C Voltage level must be set to 1.8V.

Set the Input Frequency to the PLL to 25 MHz.¶

Configure the Clock Frequencies¶

For U14, Clock 1 must be configured to 266.6666 MHz. This is the HPS DDR4 reference clock frequency. Failure to set this frequency will result in the HPS DDR4 RAM not to function. This clock should be selected in the "Enable Lowest Jitter output" checkbox.

For U15, Clock 2 must be configured to 266.6666 MHz. This is the FPGA EMIF DDR4 reference clock frequency. Failure to set this frequency will result in the FPGA DDR4 RAM not to function. This clock should be selected in the "Enable Lowest Jitter output" checkbox.

At this point, you should add the additional clock frequencies that you require.

Configure the Output Drivers¶

For all enabled output clocks, select LVDS with a 1.8V reference voltage.

Skip the phase offset inputs (no phase is required)¶

Skip the spread spectrum options¶

Export the configuration¶

Select and Save the C Code and Header File¶