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On-SoM Clock Generators

The MitySOM-A10S features two (2) programmable quad output clock generators, SI-B338B-B-GM up to 350MHz outputs, on the module. These are used to provide multiple input clocks to the Arria 10 SoC. It is possible to change the configuration of these clock generators by creating a custom binary image that can be loaded by UBoot. Please contact Critical Link () for details about this process.

The generators are pre-programmed as follows:

Clock Generator (U14)

Bus: I2C EMAC2
Address: b'1110001'
Clock Input: 25MHz +/- 30ppm (Crystal)
Voltage Level: 1.8V LVDS
Generator Output Signals Generator Output Pins Net Name Arria 10 SoC Input Balls or Other Connection Pre-programmed Frequency
CLK0A 22 REFCLK_GXBL1C_CHT_P U24 Disabled - StopLow
CLK0B 21 REFCLK_GXBL1C_CHT_N U23 Disabled - StopLow
CLK1A 18 HPS_PLL_REF_CLK_P D15 266.666666667 MHz
CLK1B 17 HPS_PLL_REF_CLK_N E15 266.666666667 MHz
CLK2A 14 REFCLK_GXBL1C_CHB_N W23 Disabled - StopLow
CLK2B 13 REFCLK_GXBL1C_CHB_P W24 Disabled - StopLow
CLK3A 10 PLL_REFCLK_OUT_N J600 12 Disabled - StopLow
CLK3B 9 PLL_REFCLK_OUT_P J600 14 Disabled - StopLow

Clock Generator (U15)

Bus: I2C EMAC2
Address: b'1110000'
Clock Input: 25MHz +/- 30ppm (Crystal)
Voltage Level: 1.8V LVDS
Generator Output Signals Generator Output Pins Net Name Arria 10 SoC Input Balls or Other Connection Pre-programmed Frequency
CLK0A 22 REFCLK_GXBL1D_CHB_P R24 Disabled - StopLow
CLK0B 21 REFCLK_GXBL1D_CHB_N R23 Disabled - StopLow
CLK1A 18 SPARE_REF_CLK_N AA16 Disabled - StopLow
CLK1B 17 SPARE_REF_CLK_P AB16 Disabled - StopLow
CLK2A 14 EMIF_PLL_REF_CLK_N P5 266.666666667 MHz
CLK2B 13 EMIF_PLL_REF_CLK_P N5 266.666666667 MHz
CLK3A 10 GXB_REFCLK1_P J4 A20 Disabled - StopLow
CLK3B 9 GXB_REFCLK1_N J4 A19 Disabled - StopLow

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