Gen 1 vs Gen 2 Dev Board Information¶

Critical Link has released two versions of the MitySOM-A10S Development Board as follows:

CL Part Number*	Generation
80-001127RC	Gen 1
80-001218RI	Gen 2

*The part number is found on the first line of the label near the PCIe header of the dev board.

Generation Differences¶

Depending on the interfaces used by your FPGA project you may need to have an alternate version to support your design on both development board generations due to the differences noted below:

Power Switch (SW701)¶

1. As all SoMs can support the 5V input type the switch was removed and pop/no-pop resistors were utilized on the dev board to set the SoM input voltage to 5V.
   1. Gen 1
      1. Switch is populated which allows for the selection between 5V VIN to the SoM or 12V VIN to the SoM
   2. Gen 2
      1. Switch is NOT populated and SoM input voltage is fixed at 5V
      2. If a 12V SoM input is required please contact Critical Link for further details.

Temperature Alert LED¶

1. A Red LED was added to the temperature alert output (t_alert) from the SoM at pin D2 of J201B
   1. Gen 1
      1. No connection to D2 at J201B
   2. Gen 2
      1. Active low red LED (D201) connected to D2 at J201B

Component Temperature Rating¶

1. Gen 1 (Commercial Temperature Rated)
   1. Some components used on the development board are not all industrial temperature rated.
2. Gen 2 (Industrial Temperature Rated)
   1. All components used on the development board are industrial temperature rated.

FMC Connector J300¶

1. It was found on Gen 1 that the P/N pair was reversed for FMC pins J18 & J19 compared to the Arria 10 SoC p/N polarity.
   1. Gen 1
      1. Arria 10 SoC Ball Y1 (P) connected to FMC Pin J19 (N)
      2. Arria 10 SoC Ball Y2 (N) connected to FMC Pin J18 (P)
   2. Gen 2
      1. Arria 10 SoC Ball Y1 (P) connected to FMC Pin J18 (P)
      2. Arria 10 SoC Ball Y2 (N) connected to FMC Pin J19 (N)

Transceivers/PCIe Connector¶

1. It was found in the Gen 1 board that the transceivers routed to the PCIe connector needed to change. Due to this, some of the transceivers connected to the FMC connector were also changed for the Gen 2 board. The differences between Gen 1 and Gen 2 are shown below and also included in the attached Excel spreadsheet (https://support.criticallink.com/redmine/attachments/download/23998/Gen1_vs_Gen2.xlsx).

PCIe Changes

PCIe Interface		Gen 1		Gen 2
PCIe (J500) Pin	PCIe (J500) Signal Name	Baseboard Net Name	Arria 10 SoC Ball	Baseboard Net Name	Arria 10 SoC Ball
A11	PERST_N	PCIE_PERSTn_3V3/nPERSTL0_LVDS2A_19p	AB11	PCIE_PERSTn_3V3/B2A_AB11	AB11
B14	PET0P	GXB_TX_0_P	AG28	GXBR TX 0_P	W28
B15	PET0N	GXB_TX_0_N	AG27	GXBR TX 0_N	W27
B19	PET1P	GXB_TX_1_P	AE28	GXBR TX 1_P	U28
B20	PET1N	GXB_TX_1_N	AE27	GXBR TX 1_N	U27
B23	PET2P	GXB_TX_2_P	AC28	GXBR TX 2_P	R28
B24	PET2N	GXB_TX_2_N	AC27	GXBR TX 2_N	R27
B27	PET3P	GXB_TX_3_P	AA28	GXBR TX 3_P	N28
B28	PET3N	GXB_TX_3_N	AA27	GXBR TX 3_N	N27
A16	PER0P	GXB_RX_0_P	AF26	GXBR_RX_0_P	V26
A17	PER0N	GXB_RX_0_N	AF25	GXBR_RX_0_N	V25
A21	PER1P	GXB_RX_1_P	AD26	GXBR_RX_1_P	T26
A22	PER1N	GXB_RX_1_N	AD25	GXBR_RX_1_N	T25
A25	PER2P	GXB_RX_2_P	AB26	GXBR_RX_2_P	P26
A26	PER2N	GXB_RX_2_N	AB25	GXBR_RX_2_N	P25
A29	PER3P	GXB_RX_3_P	Y26	GXBR_RX_3_P	M26
A30	PER3N	GXB_RX_3_N	Y25	GXBR_RX_3_N	M25

FMC Changes

FMC Interface		Gen 1		Gen 2
FMC (J300A) Pin	FMC Net Name	Baseboard Net Name	Arria 10 SoC Ball	Baseboard Net Name	Arria 10 SoC Ball
A2	DP1_M2C_P	GXBR_RX_0_P	V26	GXB_RX_1_P	AD26
A3	DP1_M2C_N	GXBR_RX_0_N	V25	GXB_RX_1_N	AD25
A6	DP2_M2C_P	GXBR_RX_2_P	P26	GXB_RX_2_P	AB26
A7	DP2_M2C_N	GXBR_RX_2_N	P25	GXB_RX_2_N	AB25
A10	DP3_M2C_P	GXBR_RX_3_P	M26	GXB_RX_3_P	Y26
A11	DP3_M2C_N	GXBR_RX_3_N	M25	GXB_RX_3_N	Y25
A22	DP1_C2M_P	GXBR_TX_0_P	W28	GXB_TX_1_P	AE28
A23	DP1_C2M_N	GXBR_TX_0_N	W27	GXB_TX_1_N	AE27
A26	DP2_C2M_P	GXBR_TX_2_P	R28	GXB_TX_2_P	AC28
A27	DP2_C2M_N	GXBR_TX_2_N	R27	GXB_TX_2_N	AC27
A30	DP3_C2M_P	GXBR_TX_3_P	N28	GXB_TX_3_P	AA28
A31	DP3_C2M_N	GXBR_TX_3_N	N27	GXB_TX_3_N	AA27
B20	GBTCLK1_M2C_P	GXBR_REFCLK1_P	PLL_REFCLK_OUT_P	No Connect/REFCLK_PCIE_P	No Connect
B21	GBTCLK1_M2C_N	GXBR_REFCLK1_N	PLL_REFCLK_OUT_N	No Connect/REFCLK_PCIE_N	No Connect
C2	DP0_C2M_P	GXBR_TX_1_P	U28	GXB_TX_0_P	AG28
C3	DP0_C2M_N	GXBR_TX_1_N	U27	GXB_TX_0_N	AG27
C6	DP0_M2C_P	GXBR_RX_1_P	P26	GXB_RX_0_P	AF26
C7	DP0_M2C_N	GXBR_RX_1_N	P25	GXB_RX_0_N	AF25