Activity
From 01/22/2014 to 02/20/2014
02/20/2014
- 04:20 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- Excellent this is a known issue. On boot the filesystem will try to calibrate the touch screen if its calibration fi...
- 03:27 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- Hello again,
Thank you for your help so far; I have been making progress, but still stuck on the NAND boot. After ... - 02:39 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Nope, if you connect it to the HPS to FPGA bridge you can treat it more like a register that the code on the HPS read...
- 01:10 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Dan,
Don't you mean connect it to the FPGA to HPS AXI bridge?
Our input data is processed in the FPGA.
Th... - 01:03 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- At that rate it might be simpler to create a FIFO in the FPGA and connect it to the light weight HPS to FPGA bridge. ...
02/19/2014
- 05:33 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Also, I'm trying to by pass the SGDMA dispatcher and use the write master directly.
Jack - 05:32 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Dan,
Our data is coming in at about 40 MHz,
Jack - 04:57 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Jack,
Looking in the SGDMA dispatcher core user guide, it appears that if you use the extended descriptors you ... - 04:33 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Dan,
Regarding the SGDMA Write Master Core. I looked through the document for this core and it doesn't give any... - 03:40 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Jack,
We do not currently have an example that uses a non-packetized Avalon stream. There should be an option in t... - 03:22 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi,
Do you have any write to HPS memory examples where I can send data into the memory in a continuous stream rath... - 08:15 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- We leave it at 300 Mhz
- 08:08 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- When you boot linux, are you changing the CPU OPP to 456 MHz or leaving it at 300 MHz?
- 08:03 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Hello,
Yes we have adjusted the bus master priority of uPP, but did not see any great improvements (strangely).
... - 07:42 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Did you check / adjust your UPP Bus master priorities?
- 07:33 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Hello,
Just a quick update. When we do not boot into linux (just uboot) we do not see
these errors.
So booting...
02/18/2014
- 08:50 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Hi Marc,
Here are a couple of other things to consider:
# In the past we've had throughput problems with TI's ... - 08:22 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- You might raise the priority up a bit (try 0 or 1). If the transfers are small, then it should be OK to give it prio...
- 08:04 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Hello,
Here are some answers to the questions:
* Are you trying to run continuous transfers?
- We do not r... - 07:17 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Hi Marc,
Are you trying to run continuous transfers?
At 75 Mhz, you should be running a buffer rep rate of 64 /... - 02:55 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Hello,
Here are some answers to the questions:
* Are you using the Critical Link MDK drivers? If so, what versi... - 07:22 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: I2C Bus
- Hi Bruce,
I believe that the I2C addresses for I2C0 are described in the "Carrier Board Design Guide":http://www.c... - We are currently investigating a problem accessing the I2C0 bus.
My initial enquiry is to find out what devices ...
02/17/2014
- 09:25 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Why is MityDSP-L138F UPP transmit sometimes giving UOR events
- Hi Marc,
If you are following the uPP design guidelines, then perhaps this is a true underflow or overflow condit... - Hello,
We use the MityDSP-L138F and between DSP and FPGA we use UPP communication but transmit (channel A) is givi...
02/13/2014
- 03:02 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Signal Tap & JTAG FPGA Programming
- Glad to hear you got it working.
Dan - 03:01 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Signal Tap & JTAG FPGA Programming
- Hi Dan,
Yes it works with the rbf file and it works when I program it in Linux. No problems there.
I managed to... - 01:58 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Signal Tap & JTAG FPGA Programming
- Hi Jack,
I've just created a wiki page for the steps that it takes to program the FPGA using the USB-Blaster, woul... - Hi,
I'm raised the issue before regarding programming the FPGA with JTAG.
I have tried programming via JTAG, th...
02/12/2014
- 04:51 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- Looking at the diff I posted the alignment prints out in both cases. This is a normal boot printout.
From your ba... - 04:00 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- Hey Jonathan,
I tried putting a few echo statement in some of the /etc/init.d scripts, but no luck. The boot is st...
02/11/2014
- 08:53 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- I would try to look to see if your nfs filesystem is trying to mount the sd card and thus causing it to hang.
Your... - 08:48 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- I removed the timestamps and did a diff between the two logs and they don't show much difference.
02/10/2014
- 02:57 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Using TI C64x+ IMGLIB on OMAPL138F"
- Hello Naveen,
As you stated, the vision_framework demo uses the IMG_sobel_3x3_16(), which you can use to understan... - 09:20 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to reserve EDMA for DSP
- I tried modifying device-da8xx.c as describe above, but the boot process hung. Here's the relevant part of the log:
...
02/07/2014
- I am running into the current error while running bitbake:
jliriano@ArmDev:~/yocto/build$ bitbake u-boot
ERROR: ... - 11:05 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- Thanks for the logs. I don't have time to look at them today so I'll try to check them out on Monday.
- 10:17 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- Hi Jonathan,
So the NFS mount on NAND boot magically started working. I don't think I changed anything. Either way...
02/06/2014
- 03:21 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to reserve EDMA for DSP
- Mary,
I think you can disable the dma usage of the spi driver. I am using the following resource declaration for ... - 11:03 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to reserve EDMA for DSP
- In researching this I found what looks like a similar problem:
http://e2e.ti.com/support/dsp/omap_applications_pro... - 03:08 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- Can you attach the full bootlog in a text file? That error is standard for kernel couldn't find root filesystem.
- 02:23 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- Jonathan,
Yes, we were able to mount the NFS root filesystem while booting from the SD card using the new MLO and ... - I am attempting to run this command to compile the kernel:
bitbake virtual/bootloader
And get the following err...
02/05/2014
- Hi All,
I can see here (http://support.criticallink.com/rm_embedded/dsp-products/MDK_DOCS/2.11/core/class_mity_d_s... - 11:01 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Latest stable linux build for MityARM-1808/F
- Thanks Mike,
That did the works for me.
Cheers,
Angelos - 06:49 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB-OTG as a peripheral and a host
- Hello Jonathan and Mike,
Thank you for your quick replies.
@Mike
Thank you for your suggestion. I could use it... - Hi,
We have received your Vision Development Kit from Digikey distributor this week. As per your VDK manual we int...
02/04/2014
- 05:22 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- Bindu,
I can't see anything wrong with your environment. Are you able to boot nfs while loading off the sd card w... - 04:18 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- Sorry about the formatting on that last post! Yeah turns out using the new files works! The files that come on the SD...
- 03:01 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- Your flashing steps look fine. Let me know if anything changes with the new files.
The new sd card image has the ... - 02:54 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- Can you edit your post and put the output inside pre tags. You can highlight text and hit the pre button above text ...
- 02:45 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- Jonathan,
Thank you for moving this over. Kernel version on the board is 3.2.0+. I used the MLO and uBoot file fro... - 08:02 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Booting from Nand
- Hi Bindu. Can you confirm that you are using a mlo and uboot that was built with the following config 'mityarm335x_4...
- Moving post for Bindu. Reference https://support.criticallink.com/redmine/boards/28/topics/1437?r=3602#message-3602
... - 02:21 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: WL1271 Calibration tool
- Greg,
Have you been able to get the wifi calibration tool running on the evaluation board?
Thanks
Jesse - 01:50 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- Mary,
You can search the kernel source for the messages by using grep. For example I might search for the string ... - 01:18 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- I have successfully added the SPIDEV support to the kernel and can communicate over the bus now.
I occasionally se... - I am having an ARM/DSP conflict. The DSP is primarily reading data from the McBSP and transferring the data to a cir...
- 12:39 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Latest stable linux build for MityARM-1808/F
- In the "file tab":https://support.criticallink.com/redmine/projects/arm9-platforms/files there are MDK downloads (.ru...
- Hi All,
Could you please tell me what is the Latest stable linux build for MityARM-1808/F? Could you also provide ... - 08:53 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB-OTG as a peripheral and a host
- Probably the best solution would be to load in the USB OTG file storage gadget. This will make the L138 look like a ...
- 08:33 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB-OTG as a peripheral and a host
- Unfortunately I don't have any experience with interfacing with Android phones. If your Android phone supports rndis...
- 05:14 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: USB-OTG as a peripheral and a host
- Hello,
I have used RNDIS and have been able to transfer data.
However, I would also like to know how to use eithe... - 07:50 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Flashing NAND from SD Card
- Hi Bindu,
A lot has changed since this post was made. I've created you a separate thread that references this one...
02/03/2014
- 07:44 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Flashing NAND from SD Card
- Hello,
Has there been any progress on this? I followed the instructions on this page: https://support.criticallink... - Posting on behalf of a customer:...
- Hi,
I need to set up multicast routing between two interfaces on the mity board running Angstrom linux 2.6.34
...
01/31/2014
- 01:42 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: MityARM Kernel Versions, TI SDK and PSP Questions
- 1. The CL and TI website suggest Ubuntu 10.04 LTS, but the LINUX kernel version is 2.6.37. How is possible to build 3...
- Posting this on behalf of a customer:...
- 05:14 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Regarding handling UART on MitydspL138F(OMAPL138)"
- Hi,
We are trying to interface Second UART (J504 as you mentioned) with Atmel AtXmega Controller so that upon rece...
01/30/2014
- 02:22 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Regarding handling UART on MitydspL138F(OMAPL138)"
- Naveen,
The first UART is used for the debug/console port, UART1.
You would like to use the second UART in your... - 01:17 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Reagrding spi NOR flash memory updating"
- Naveen,
I'm assuming that the question here is how would you get the updated Kernel from your host PC onto the Mit... - 10:01 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Ethernet
- Edited my response. Good eye Dave. Thanks!
- 09:31 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Ethernet
- Greg,
Only 2 "e"s in setenv, not three... Jack probably knows that, but just to be clear...
Dave
- 09:10 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Ethernet
- Hi Jack,
Follow these steps to correct the ethernet:
1. Break into u-boot by resetting the system and hitting ...
01/29/2014
- 06:48 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Ethernet Rev B
- Hi,
I just received your rev B module. We noticed that the ethernet doesn't work on this revision at all. Is there...
01/27/2014
- 12:56 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Hi Jack,
I'm not sure what else to try other than trying to program the FPGA through a JTAG pod, which I believe y...
01/24/2014
- 01:57 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Hi Dan,
I did what Adam suggested and it made no difference. I tried it without anything plugged in and still noth... - 01:21 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Currently I do not believe that is the case, seeing as this problem is happening in both uboot and linux.
Have you... - 12:28 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Could this be a OS issue that's causing it?
Can some one direct me the exact link where I can download the img fil...
01/23/2014
- 06:18 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Memcpy data transfer error from FPGA address space to CMEM-allocated data buffers.
- Hello Mike,
I've solved the problem! Actually it was a timing problem related to the access policy to the emif.
... - Hi Sir,
This is regarding editing the kernel in NOR flash memory, a detailed steps have been given in wiki for edi...
01/22/2014
- 03:37 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Your MSEL is currently 00000. Try changing S100-position3 to OFF to get an MSEL[4:0] of 00100. This will change the ...
- 03:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Looking through the uboot source code it seems that the HPS is not able to set the FPGA into a reset mode. Which coul...
- 02:57 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- correct
- 02:56 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Is the following the full error you received?...
- 02:34 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Yes
- 02:33 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- was this from the **run fpgaload**?
- 02:31 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Hi Dan,
I got an error: Failed with error code -1.
Jack - 02:29 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Hi Jack,
This needs to be run during uboot, which you get to by pressing any key during the first 5 seconds of sta... - 02:13 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Hi Dan,
The Linux OS on the board doesn't have run and saveenv. I tried to update it, but it doesn't have the apt-... - 01:33 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- ...
- 12:59 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Hi Dan,
Regarding the uboot procedure, I have never worked with uboot before and the instructions on rocketboard i... - 12:33 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Hi Adam,
I'm not sure what the default positions for the MSEL or which of the switches on board are for the MSEL. ... - 12:23 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Hi Jack,
Please check the MSEL dip switches. These should be set to FPPx16 or FPPx32 for the FPGA Manager to be a... - 12:07 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Hi Dan,
The same issue still occurs after power cycling.
I'm wondering if it's a hardware issue.
Jack - 10:43 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Load FPGA Timeout Error
- Hi Jack,
We have not seen this issue yet. If you power cycle the board did this issue still occur?
Dan - 09:19 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Memcpy data transfer error from FPGA address space to CMEM-allocated data buffers.
- Dear Mike,
When you say to configure the emif wait states etc., you mean modifying, for example, the file "u-boot-mi...
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