Activity
From 06/29/2014 to 07/28/2014
07/28/2014
- 03:13 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Start Guide : Cannot build helloworld application with eclipse
- I'm working through the Starter Guide for the MityDSP-L138 configured with
- VirtualBox 4.3.0 (could not get Mity... - 11:55 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: I2C 0x8 Address
- Looks like the kernel is configuring the OMAP-L138 I2C slave address as 0x08 (by default, it is 0x00 - illegal - in t...
- 11:33 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: I2C 0x8 Address
- No worries. I don't think i2c-detect does anything strange with this address. By looking at the code, I don't see any...
- 11:29 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: I2C 0x8 Address
- We're looking at it now. I think that the i2c-tools may be emulating SMBus and trying to run the arbitration scheme ...
- 10:49 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: I2C 0x8 Address
- Source : System Management Bus (SMBus) Specification Version 2.0 August 3, 2000 :Appendix C – SMBus device address as...
- 10:20 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: I2C 0x8 Address
- OK. So is it a defect on the MityDSP-L138F board, or is it the address of the OMAP I2C bus?
- 09:54 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: I2C 0x8 Address
- Also on a devkit where the dvi chip was removed the 0x08 address still appears....
- 09:52 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: I2C 0x8 Address
- Well at the least I can identify the others. 0x38 is the dvi chip, 0x48 is the pmic, and 0x50-58 is the eeprom. Whe...
- 09:31 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: I2C 0x8 Address
- We use a custom baseboard, but the address 0x8 is at the the industrial IO development kit as well:
root@PureVLC:~... - 08:06 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: I2C 0x8 Address
- Did you set the pin-mux settings for the I2C1 lines on the second device in the kernel as well? For the devkit baseb...
- 07:59 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: I2C 0x8 Address
- The problem is that if we enable both I2C interfaces by changing the linux source code by adding the following lines ...
- 07:55 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: I2C 0x8 Address
- What are you using for your baseboard?
- 07:46 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: I2C 0x8 Address
- I am using MityDSP-L138F board.
- Hi All,
When I run i2cdetect -y 1 I get the following output:
0 1 2 3 4 5 6 7 8 9 a b c d e ...
07/25/2014
- 02:42 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: PCI-e Device Driver - munmap related error
- Can you post your code? Are you getting user space faults and not kernel oops, right?
Are you unmapping with the ... - Posting on behalf of a customer:
I'm having some sporadic problems with the device driver I made for our pci-e dev...
07/24/2014
- 09:05 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
- Hi Nigel,
I don't believe there is a way to do it directly in QSYS. You may be able to patch your generated outpu... - 07:59 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
- Hi Adam,
Thanks for the insights.
Do you know how to persuade qsys to run the DDR at a slower speed? In normal ...
07/23/2014
- 11:06 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: fpgautil read Issue
- Hi Mike,
I found the issue. I was updating the edo_out signals only when rd was going high.
From the waveform... - 08:42 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: fpgautil read Issue
- Can you post (or email me) you VHDL source related to the loopback register?
Do you have Chipscope? It might be w... - I'm using MityDSP-L138 Board. I have implemented a Custom IP in the FPGA board.
I'm using the CS5 ARM Chipselect ... - 04:19 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
- Hi Nigel,
You are correct, the C8ES devices do not meet timing with the FPGA DDR according to Quartus. The ES sil... - Although your reference design using FPGA DDR compiles as supplied, when I select the correct device (5CSXFC6C6U23C8E...
07/22/2014
- 11:42 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- Hello Silvano,
No, the MDK uPP libraries are not setup to work with the debugger. In your code you can try settin... - 08:54 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- The strange behaviour still continue.
When we do not send data to uPP using the FPGA the program does not have the s... - 03:10 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- Thanks a lot for the suggestion.
I will check with my colleague the VHDL connection.
I also had a check at the opti...
07/21/2014
- Hi,
I'm using the pre-dev MitySOM eval board and I'm trying to rebuild a complete working environment with the cu... - 12:41 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- The strange stepping sounds exactly like when optimizations are turned on.
- 11:46 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- I'm not a VHDL guy, so I can't say whether this will work as you have it. It sounds like you and your VHDL guy shoul...
- 11:34 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- Here you can find the VHDL sources.
I cannot help you a lot with VHDL becuse it is developed by a colleague of mine.... - 11:19 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- Thanks a lot.
Now the working principles are clearer.
The problem now is that the software has a strange behaviour.... - 11:09 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- Each time you call receive, a DMA is set up to fill the buffer you pass. Once that DMA completes, no data will be tr...
- 10:08 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- Ok thank you.
I will try to change all the interrupt levels.
Another question is: but once the buffer is filled? Wh... - 10:05 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- I don't see any reason that it wouldn't work, but I have seen issues with some interrupt levels not working. I stron...
- 09:59 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- Thanks to have a look.
I have the signal enable and start always active.
I think that therefore is right to set bCh... - 09:49 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receiving problem
- A couple of things that I see are different from some code that I have working here:
I use nHWInterruptLevel = 7. ... - Dear all,
I am trying to use to uPP to receive data coming from the FPGA.
Attached you can find the code I wrot...
07/20/2014
- Hi,
I originally wanted to connect to the board either usb storage peripherals or webcams-like peripherals. I bou...
07/17/2014
- 05:08 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pre production (-X) modules with newer sd image
- That update to the conf/local.conf should fix the uImage issue. As for the building of the DTB through yocto, we push...
- 03:42 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pre production (-X) modules with newer sd image
- Thanks a lot for the feedback.
I have noticed that the Yocto wiki has just been updated concerning the uimage format... - 09:13 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pre production (-X) modules with newer sd image
- I am currently working through the kit and having a similar experience. The following seems to work for me in regard ...
07/15/2014
- 06:28 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pre production (-X) modules with newer sd image
- Well, the orange LED switches OFF because with this new version of the SD card, the FPGA is loaded with a firmware at...
- 04:39 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi Jonathan,
Thank you for your patches, it's working for me!
I have applied and successfully rebuilt my kernel.
...
07/14/2014
- 11:39 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Ngoc,
Can you confirm that this is working for you and i'll move the changes into our main kernel branch?
I als... - 10:51 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- gpioToggle test passed when i just ran it. Not sure why....
- 10:24 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Reran some of the commands to see which fail. The ./PRU_memAccessL3andDDR can cause system segfaults as it appears t...
- 09:11 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Running through all the examples, atleast one of them seems to have caused a system segfault as not even reboot was a...
- 09:09 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi Ngoc,
I have been working on getting this to work. So far i've integrated the patches which i've posted to a t... - 04:45 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi,
Thank you, I'm waiting for your patches. ^^
Regards,
Manh BT - 09:43 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Yeah by using the ti_ 335x include files I was hoping to greatly simplify our config file. Hopefully it hasn't cause...
- 09:31 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Ok,
I knew it had to be in there somewhere, was just a bit confused
as the original mityarm335x.h had a nice ... - 09:26 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Pretty sure I found "#define CONFIG_SPI" in one of the ti_ config files that get included.
- 09:25 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Yes the Micron N25Q00AA does support the 48Mhz clock. The sf erase still seems longer
but I'll need to time it get ... - 09:25 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- I have been looking into this. It seems that it was a mistake as the added resistor isn't mentioned in our Engineeri...
- 03:28 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- OK, the cable that I used was a miniAB to USB A plug which was then attached to a USB A to USB A gender changer (a li...
07/13/2014
- 10:18 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hello Manh BT,
The patches Mike described are in the mainline Linux kernel (http://kernel.org/). You can search fo... - 09:42 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi Michael,
Thanks for your information, but where can I get above patches? Is it in Critical Link MDK ?
Regard...
07/11/2014
- 05:26 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Also make sure your Nor chip supports 48Mhz on the spi bus.
- 05:25 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Did you notice any time difference with the slower speed?
- 03:30 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- I took out the CONFIG_SPI_FLASH_BAR define and it now seem to pass the long erase command.
-----------------------... - 02:23 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- It may be perfectly fine with the generic name then.
Try changing the spi clock speed and see if you get different... - 02:19 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- I added the CONFIG_SPI_FLASH_BAR define to mityarm335x.h and the warning is goes away on the "sf probe" command.
I a... - 01:38 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- 1) I'm not sure why its detecting it differently. Maybe the newer u-boot has a more specific driver for this chip?
... - 12:44 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Hey Johnathan,
Testing out the new spi bus changes seem fine. I do have two quick questions:
1) The original... - 01:30 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- As per the On-The-Go spec, the mini USB adapter is supposed to tie the USB_ID pin to GND to indicate it should be put...
- 12:36 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- Yep, loading an image seems to be OK. Next week I'll try the whole image + rootfs and make sure that works too.
T... - 12:20 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- OK, now I get it. There's no resistor on my board pulling the ID pin down to 0V. I've just put a link between pins ...
- 12:07 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- The number is 80-000286RI-2
REV B
S/N 132556
Which bootloader are you using? I've been using my own compilation... - 12:05 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- Whats the part number of your dev kit? Should be a 80- number.
- 12:03 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- I just tested this by first plugging the flash drive into the full size usb port J102. With no luck. Then plugged d...
- 11:43 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot and USB using L138F SoM
- I forgot to say that I know that the USB port works because, once in Linux I can mount the drive OK and read/write fi...
- Hi there,
I'm using the L138F SoM on a REV B Industrial I/O board and I am trying to boot from a USB drive. uBoot i... - 09:34 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Building u-Boot and Preloader
- I believe that the files in question need to be copied from software/spl_bsp/generated into u-boot-socfpga/board/cl/m...
- 08:31 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to enable PRU Subsystem on MityDSP-L138F SOM ???
- Hi,
I think we need to add the following patches (from linus tree) to the kernel to instantiate the PRUSS drivers ... - Hi everyone!
I'm using MityDSP-L138F SOM + IO Industrial Board and now trying to work with PRU subsystem of OMAP-L...
07/10/2014
- 05:10 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- The skipping bad block is not an error but more of an info. Blocks can be marked bad from factory and during use. T...
- 04:19 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- The clock is working now. Thank you.
But when we flash the nand, there is an error:
root@mityarm-335x:~# flash_... - 03:29 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- So if this is the problem I'm thinking of. It was discovered that when we changed to the 3.2 kernel we weren't setti...
- 03:26 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- Hey Jonathan,
Thanks again, we will definitely try this solution and let you know if it works. I would like to kno... - 03:00 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- I've attached the lastest uImage but yes you can build it if you would like. Instructions are here [[Linux_Kernel]]
... - 02:57 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- NAND read: device 0 offset 0x340000, size 0x500000
Skipping bad block 0x00780000
5242880 bytes read: OK
## Bootin... - 02:56 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- We used the pre-build kernel image that came with the board. The kernel that in the Virtual Machine/home/mitydsp/proj...
- 08:12 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- What version of the kernel came with your devkit? Could you post a boot log?
Particularly I want to know if your ... - 02:23 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Breaking changes on early MityARM
- Should have spotted that note but somehow managed to miss it!
Thanks,
Nigel. - 02:00 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Breaking changes on early MityARM
- Hello Nigel,
Sorry about that. The description of the hardware changes for the Dev Kit baseboard are here:
htt... - I have an early MityARM module and dev kit. On trying to implement the latest software versions I found that the Ethe...
- I am just revisiting the development kit after working on other projects and I am trying to locate the copy_files.sh ...
07/09/2014
- 05:12 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Just pushed a fix for this.
http://support.criticallink.com/gitweb/?p=u-boot-mityarm-335x.git;a=commit;h=82762ccda72... - 04:33 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- Here is our clock tree (in /sys/kernel/debug/clock/summary):
clock-name parent-name ... - 04:14 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- When we boot into Linux and use the "date" (system clock) and "hwclock" (RTC I assume) commands to set/ask for time, ...
- 08:02 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: Time drift
- Hi,
What do you mean by "hardware and software" clocks. Are you using the RTC or just the system clock? Can you ...
07/08/2014
- Hello,
We bought a MityARM335x dev kit months ago. We have noticed that the time on the board (both software and h... - Hi,
I'am just starting to discover the eval kit. The one I ordered from Mouser was a pre-prod (- X) version. I und...
07/07/2014
- Hi,
Do you have sample c/c++ program to read/write a memory inside Cyclone V FPGA through hps2fpga bridge interfac...
07/03/2014
- 05:14 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Hi Bill,
Sorry for the confusion. The latest image updated the Baud Rate to 115.2kbps to be consistent with the r... - 05:05 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Hi,
I downloaded the sd_image_mitysom_5csx_rev1B.zip, and extracted out the .bin file. Then I typed "sudo dd if=sd... - 02:45 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- It was a cache invalidation issue. Calling BCACHE_wb() solved the problem.
I did find a small bug in the trasmit()... - 08:29 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- My first thought on seeing this is that it is probably a cache issue. After you set the values in the buffer, the va...
- 11:16 AM MityDSP (TI TMS320C6xxx Based Products) Software Development: RE: Problem compling with the MDK, unresolved symbols
- I got a similar problem reported here.
https://support.criticallink.com/redmine/boards/8/topics/4002
Can someone he... - Dear all,
I have a problem with Code Composer 6 and my DSP/BIOS project (called "quadra").
I have a first file (c...
07/02/2014
- 09:27 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Information on how to make an SD card based upon the current Development Kit SD card image (Rev 1B) can be found on t...
- 06:17 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Mike,
I think you meant "memtool -32 0xFFD0501C=0x06" for brgmodrst register. The reset value of the register some... - 08:52 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- For reference on the reset register:
http://www.altera.com/literature/hb/cyclone-v/hps.html#reg_default_component/... - 08:51 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocol
- Hi Bill,
It looks like you are using version 3.8 of the kernel. Version 3.8 does not have the FPGA bridge drivers... - 06:47 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- We cannot get the uPP to work. For test we just use the FPGA to pass the uPP pins to FPGA output pin. The Enable pin ...
- 07:19 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- Ah, yes, I am sorry I forgot about the EMIFA scheduling delays. You are correct.
If you are using the reference P... - 12:55 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- We started with EMIFA. We got a delay of 11uSec between transfers as discussed in this post:
https://support.criti... - 11:49 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linker error on DSP application with Code Composer 6
- Thanks a lot to everybody.
It was a simple linker problem.
Silvano - Hello everybody.
We see an unexpected behaviour during simple debugging operations.
/*
* main.c
*/
#incl...
07/01/2014
- 04:30 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linker error on DSP application with Code Composer 6
- Note i found the generic c674x device under target: generic devices
!DSP_C674x.png! - 03:39 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linker error on DSP application with Code Composer 6
- Silvano,
Have you followed our guide to building a Hello World application?
https://support.criticallink.com/re... - Dear all,
we are trying to build a simple application on DSP using Code Composer 6 plus DSP/BIOS.
In the followi... - 09:49 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- U-Boot# sf probe 0:0
SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff
Failed to initialize SPI flash... - 09:49 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Jonathan,
I checked with manufacturing and they do use the command in verification
of basic communication wit...
06/30/2014
- 05:06 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Following your lead and my hardware engineers suggestion we did a temporary check and set 0x44E00050
(CM_PER_SPI1_C... - 05:03 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Committed change.
http://support.criticallink.com/gitweb/?p=u-boot-mityarm-335x.git;a=commit;h=bc7833792442421a60e74... - 04:54 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- I'm testing this change right now and am going to push a commit if it works.
- 04:48 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Thanks. Let me take a look and if it works.
- 04:45 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- I think I found the problem. The memory address 0x481A0000 refers to McSPI1 and only spi0 is enabled in the u-boot.
... - 04:40 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- We had originally set up to boot out of SPI NOR and on occasion do use that ability for
manufacturing testing. The ... - 04:16 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- No since booting from the spi nor on our SoMs doesn't work and I wasn't aware of anyone using the nor, I didn't look ...
- 03:40 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: SPI clock issues with using newest u-boot
- Hey Jonathan,
Looking at your release without any of my mods, serial NOR was removed (no sf commands.) Was ther... - 04:18 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- Have you tried just writing to the FPGA via EMIFA? That would be a 16 2-byte word transfer. Even with 10 wait state...
- 03:11 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP delay between transmissions
- Re-architecting our code is not really a vaiable solution. We have a feedback loop running in the DSP, that depends o...
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