Activity
From 08/26/2012 to 09/24/2012
09/18/2012
- MW 05:42 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- See Table 1 in the "datasheet":http://www.mitydsp.com/images/upload/File/MityDSP-L138F%20Spec.pdf. The pins are tagged with an asterix and a note at the bottom of the table. But yes, those are the 8 pins.
-Mike
- MM 12:10 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Mike,
I didn't realize that the DVI wouldn't work with the LX-45, luckly we don't need the DVI interface. For reference are the 8 pins missing for DVI the only pin difference between LX16 and LX45?
Thanks,
Matt - CO 10:18 AM Software Development: RE: Simple GPIO toggle
- It works! Thanks for all your help on this Mike. I really appreciate that.
Big Note: It still does not work on Gpio0/7. Because gpio0/7 is not actually routed to the J700 connector!!!
Look at the links for the latest rev of the boa... - CO 08:56 AM Software Development: RE: Simple GPIO toggle
- My board is rev: 80-000268RI-2B, the latest revision.
Ah yes. I see. I really should have spotted it myself as I went and checked GP0[7] in the L138 docs and saw that it was multiplexed with PWM and mcASP functionality. But as GP0[6] ... - MW 07:21 AM Software Development: RE: Simple GPIO toggle
- Hi Conor,
Think I found it. If you check the schematics from this "page":http://support.criticallink.com/redmine/projects/indio/wiki/Industrial_IO_Revision_Information, it looks like GP0_7 is pin-muxed for the AXR15 (done in the base... - CO 05:56 AM Software Development: RE: Simple GPIO toggle
- I took the MDK from 2012-03-12 and compiled uBoot and uImage from defaults (using industrialio-defconfig for the kernel). I then flashed those to the board and it booted up just fine. But GPIO0/7 will still not toggle. It will change gpi...
- CO 03:51 AM Software Development: RE: Simple GPIO toggle
- I cannot find any particular reason for the pins to do this in the code. I'll recompile the kernel and uboot on the off chance something is happening there... I never updated uboot and I believe some gpio pin parameters are set there too.
09/17/2012
- MW 07:29 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Matt,
Are you sure you have an LX-45 based FPGA? The LX-45 does not bond out 8 pins that the LX-16 does. These include pins F12, E12, D12, C12, F11, E11, E7, and E8 (this should be documented in the specification). All of this sign... - MW 07:09 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Matt,
Are you using a wide screen monitor? We've seen some widescreen monitors won't lock up with VGA resolution due to the aspect ratio. You might try using the wvga_800x480 setting instead (that is the resolution that the visio... - MM 06:32 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Mike,
Yes, I am using the DVI connector. The FPGA image I am using is one I generated for the x45 FPGA from the source code in examples/industrial_io/fpga. I though this code was for the vision framework kit and would have support ... - MW 05:58 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Matt,
If you are trying to use the DVI connector, you need to use the FPGA image that was built to run with the DVI interface and not the LCD interface. The builds are different as the clock rates and pin-outs/routing are not the ... - MM 05:42 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Ok good news! I got the FPGA bin files needed so that the FPGA ready light comes on. The not so great news is I can't get anything to show up on the monitor connected to the industrial_io board.
I'm following the instructions from:
... - MM 10:11 AM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Mike,
Last week I didn't really have time to work on it, this week I'll know if I need more assistance.
-Matt - CO 08:46 AM Software Development: RE: Simple GPIO toggle
- That's supposed to be GPIO0/6 by the way...
- CO 08:44 AM Software Development: RE: Simple GPIO toggle
- Certainly... The PCB number is "120540". I've no boards plugged in at all - just the L138 module and the baseboard. There's only a single wire pushed into the connector which is connected to a voltmeter.
I'll try another one.....
O... - MW 08:39 AM Software Development: RE: Simple GPIO toggle
- Hmmm...
Do you have an expansion board plugged in right now? Can you disconnect it if you do?
It's possible that the outputs might not match the inputs if there is an external driver or short that is stronger than the driver in th... - CO 08:29 AM Software Development: RE: Simple GPIO toggle
- GPIO0/15 is the opposite which is rather odd. It starts out as 0, whereas GPIO0/7 starts out as 1:
root@mityomapl138:/sys/class/gpio# cat gpio15/value
0
root@mityomapl138:/sys/class/gpio# echo "out" > gpio15/direction
root@mityomap... - CO 08:21 AM Software Development: RE: Simple GPIO toggle
- Thanks Mike,
When I cat from /sys/class/gpio7/value, it reads "1" all the time, no matter what I've previously written. I did think that I was reading from the wrong pin so I had checked that...
The board is a L138F in an Industria... - MW 07:23 AM Software Development: RE: Simple GPIO toggle
- Hi Conor,
I don't see anything wrong with your approach. You might check the value that the pin is reading back (e.g., cat /sys/class/gpio7/value). If the pin is stuck, it should right a "1" in all cases. If it is toggling, then per... - I see this has been asked before in various ways so sorry to ask again (I'm not getting it!).
I have pin 19 from J700 hooked up to a meter. The MityDSP docs say this is GPIO, bank 0 offset 7.
So I should be able to toggle the pin b...
09/16/2012
- Like to seek your help on an uPP related question. I plan to burst out I and Q data from memory using the two uPP channels to the FPGA. In fact, I plan to drain most of the 256MB RAM using multiple DMA calls (if required). I see from ...
09/15/2012
- MW 06:56 AM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Matt,
Did you get through this, do you still need assistance?
-Mike
09/14/2012
- FT 06:24 PM Software Development: RE: Problem with uPP in DLB
- Greg,
Thanks for answer.
By the way, do you have a dummy FPGA load (in .bin format) that output "known fake data" on uPP?
It can be very very very useful.
Thanks!
-François - GG 05:15 PM Software Development: RE: Problem with uPP in DLB
- François,
Glad to hear that fixed your problem!
In regards to your follow up question, yes, you will most likely need to invalidate the cache on your receive buffer each time before passing it into the DspUpp receive function in ...
09/13/2012
- FT 02:43 PM Software Development: RE: Problem with uPP in DLB
- Greg,
You was right on and you make my day!
Now, I have another question regarding the cache. I used the uPP in DLP mode for uPP driver integration. However, it is a temporary solution because our FPGA is not yet ready. When our FP... - GG 02:24 PM Software Development: RE: Problem with uPP in DLB
- Hi François,
We have not done any work with running the system in digital loopback mode. The fact that you are getting a response back and not just hanging on the receive mailbox is a good sign. The pinmuxing should not matter as dig... - I am trying to use uPP in DLP mode with an MityDSP1810F board but my rx buffer is still empty after a "ransaction.
I am using modified version of DspUpp.cpp file.
Here code snipped
*buffer.c*
09/12/2012
- We are using uPP in our design - UPP XDx signals & BOOT function are muxed, what must I do?
- I am actually design an eval board using your L138 module. I am wondering if I need to care about the BOOT pins (muxed with others fonctionalities), so that your L138 module will properly boot, or is that done within your L138 module.
D...
09/11/2012
- We need to switch power off to the entire card based on USB activity.
Any easy way to do this?
Also how long is the boot time to load the OMAP code and FPGA code from NVRAM from power up to being able accept commands from the USB? - MW 03:27 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- It's the same thing. It got branded with two names early on. Profibus really only works with the MityARM-1810, as there is a licensing restriction on the PRU microcode that runs the profibus stack. You can evaluate it using the other ...
- MM 02:38 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- I guess now is a good time to ask, I'm not sure industrial I/O devkit or the PROFIBUS Development Kit, or if there is even a difference between to two. This question came up before and I guess we might as well just ask the expert.
Th... - MW 12:07 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Matt,
All of the images on the example site are for an LX16, which (I thought) was the standard size FPGA for modules delivered with the Industrial I/O DevKit boards. The images for the LCD on the wiki page are for LX16 based modu... - MM 11:56 AM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- *Edit*
The board acually says REV A, not sure if it matters. - MM 11:52 AM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Ok, thanks Mike. I'll be sure to check out the newer branches. I was able to get fpga_ctrl to load using the uimage from the MDK folder.
I had a few more questions about getting the screen to work.
I can't seem to be able to get th... - MW 07:23 AM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Matt,
There are several branches on our git server. The "master" is somewhat older, which is your 2.6.34-rc1. The newer MDKs use different branches. Most use the mitydsp-linux-v3.2 branch. You can check that version of the kern... - MW 02:00 PM PCB Development: RE: Usage of GP0 pins on MityDSP-L138F (Posted on behalf of a Customer)
- The "datasheet":http://www.mitydsp.com/images/upload/File/MityDSP-L138F%20Spec.pdf for the MityDSP-L138F contains this information. Perhaps it is not clear?
Table 1 in the datasheet lists for Pin-Out for the SOM. For the pins labell... - My programmers need to know:
What (if anything) is connected to the GPIO pins on port GP0 onboard the MityDSP-L138F board.
What we want to hear is that the CPU GPIO pins are wired only to the pins of the 200-pin SODIMM connecter, and...
09/10/2012
- MM 10:05 AM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Mike,
If I understand what I am doing correctly, I am using version 2.6.34-rc1 and I got the kernal from git://support.criticallink.com/home/git/linux-davinci.git.
Thanks,
Matt
09/07/2012
- MW 06:40 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Matt,
The error messages you are getting are from the kernel module files not being compiled against the same version of the kernel. Newer filesystems have udpated kernel module files (the ones on the wiki are admittedly pretty ol... - Hi,
I've been working with our MityDSP L138F and devolopment board for a few days, today I tried to follow the insturctions to configure the LCD (http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/LCD_configuration)
... - SW 09:49 AM Software Development: RE: kernel build
- duh, I guess it helps to execute the instructions you guys post. After tftp'ing the new kernel I would just type boot at the prompt and then boot up the kernel in flash. I was able to get the new kernel to boot this morning. sorry abo...
09/06/2012
- TC 05:59 PM Software Development: RE: kernel build
- Scott may have found the issue ... he is going to verify and re-post ...
- Hello, I am trying to build the kernel to support EXT4 filesystems. I have downloaded the latest configuration MDK_2012-08-10. I run the menu config with the default config file. The menuconfig displays Linux/arm 3.2.0 Kernel configur...
09/05/2012
- MW 03:03 PM Software Development: RE: L138 SD Card Boot & AISgen
- I don't have a bunch of time to wander off on this, but you might check the the DEVICE_INIT() routine of the $MDK/sw/3rdparty/OMAP-L138_FlashAndBootUtils_2_27/OMAP-L138/Common/src/device.c file. This has the PLL and DDR initialization c...
- RM 02:44 PM Software Development: RE: L138 SD Card Boot & AISgen
- Hi Mike,
Thanks for getting back to me so quickly.
We are indeed using a non-FPGA SOM. We have DIP switches on our baseboard to let us set the Boot[4..1] pins and changing these certainly changes the boot behaviour. Pull-ups are 1k... - MW 01:15 PM Software Development: RE: L138 SD Card Boot & AISgen
- Hi Richard,
Can you confirm you using a SOM without an FPGA?
FPGA based SOMs do not expose the bootmode / bootconfig pins necessary to boot directly out of SD. Those modules only support booting from SPI NOR or from UART via the... - Hi,
We're trying to create an SD card that contains both u-boot and our Linux kernel for an L138 module. We've now got our own baseboard, but it is very similar to the IndustrialIO board.
I've read the TI wiki pages on SD boot (htt...
09/04/2012
- EB 04:32 PM FPGA Development: RE: Voltage of bank 3 on MityARM 1810F
- Thanks for the quick reply!
- MW 04:16 PM FPGA Development: RE: Voltage of bank 3 on MityARM 1810F
- No that is a typo in the UCF file. The voltage is really 1.8V.
Those lines in the UCF should be as shown below. I thought we had corrected that in the BSP packages, looks like the errors are still there. Sorry Emmett. - EB 03:58 PM FPGA Development: RE: Voltage of bank 3 on MityARM 1810F
- Are these lines truly connect to the AM1808 as implied in the UCF?
- I started my FPGA code using fpga/vhdl/MityDSP_L138.ucf
I want to add to the design io_gp8(15 downto 8).
These lines are commented out in MityDSP_L138.ucf but the IO is 1.8V.
NET "io_gp8<15>" LOC = "T1" | IOSTANDARD = LVCMOS18;
1....
08/31/2012
- JP 09:58 AM Software Development: RE: Debugging DSP in VirtualBox?
- The Spectrum Digital XDS510 USB emulator pod does not seem to be useable from within the current Oracle VirtualBox.
08/30/2012
I followed the procedures of "Installing Open Embedded Core", no problem from step 1 to 4, but at step 5, there's no ~/.oe/environment-oecore file, how to create the file?
I flashed Angstrom v2012.05 - Kernel 3.2.0 to my mitydspL138...
08/28/2012
- CO 07:08 AM PCB Development: RE: MMCSD
- Sorry, I meant GPIO_0[6 or 7 or 13 or 15] as they are on the J700 connector along with MMCSD0...
- CO 04:16 AM PCB Development: RE: MMCSD
- Ah yes, that makes sense - I forgot about the degree of pin muxing going on in the L138 and the UPP would make sense there. My design is based around the WL1271 as well actually, although I've no reason to suppose a TXB0108 wouldn't do t...
08/27/2012
- MW 07:06 PM PCB Development: RE: Used EMIFA-Signals/Pins
- Yes, there should be several.
The only interface on the EMA on the modules with non-FPGA pins is the NAND (x8, but the upper 8 bit lines should probably be left alone). The NAND interface uses the following signals:
EMA_D(15..0)
... - CR 06:48 PM PCB Development: RE: Used EMIFA-Signals/Pins
- This is the mainquestion: Are there some not used Pins of the EMA interface which i can use as GPIO and keep the onboard memory working at the same time?
I need the GPIOs on the EMA-Pins, because i wanna connect some devices to the dev-... - MW 11:13 AM Software Development: RE: Vision Development Kit - What toolchain?
- Any of the ARM side GCC toolchains released should work with the VDK. I would recommend using the most recent one distributed.
The DSP side, I believe, was compiled with CGT 6.1.19, but any version 7.0 chain should work.
-Mike
- MW 10:28 AM PCB Development: RE: MMCSD
- Hello Conor,
Some background: the MMCSD1 was routed through the FPGA because it is pin-muxed with the UPP channel 0, which gets used quite a bit by our customers to push acquisition data from the FPGA into the OMAP-L138 processor. Ou... - Hi all,
I was looking at interfacing a wireless module to the MMCSD ports on the MityDSP L138F module. There are two ports available - one out to the dev board and one to the FPGA. The dev board is 3.3V LVCMOS but the module I have in...