Activity
From 09/06/2012 to 10/05/2012
10/05/2012
- MF 11:20 AM Software Development: RE: DSP Hello World won't link
- Almost ...
In Eclipse in Properties->C/C++ Build->Settings->Cross Settings I changed Path to "/usr/local/oecore-i686/sysroots/i686-angstromsdk-linux/usr/bin/armv5te-angstrom-linux-gnueabi" as you suggested. Still did not compile.
... - GG 10:56 AM Software Development: RE: DSP Hello World won't link
- Hi Mary,
In Eclipse in the Properties->C/C++ Build->Settings->Cross Settings try setting Path to "/usr/local/oecore-i686/sysroots/i686-angstromsdk-linux/usr/bin/armv5te-angstrom-linux-gnueabi" (And make sure that Prefix is set to "ar... - DG 10:54 AM Software Development: RE: DSP Hello World won't link
- Hi Mary,
Your PATH would need /usr/local/oecore-i686/sysroots/i686-angstromsdk-linux/usr/bin/armv5te-angstrom-linux-gnueabi/ prior to running Eclipse for it to locate the compiler. I think you can also edit the C++ environment within ... - MF 10:44 AM Software Development: RE: DSP Hello World won't link
- Sorry, there was no such entry in ~/.bashrc nor in /etc/bash.bashrc
I think there is something amiss in my Eclipse settings. I noticed that the newer toolchain releases extract to a different directory structure than the older ones. ...
10/04/2012
- GG 03:28 PM Software Development: RE: DSP Hello World won't link
- Hi Mary,
My guess is that somewhere (most likely your bashrc script) the environment for the old toolchain is being setup and that is why even after running the setup script for the new toolchain you still see gcc as version 4.4.3.
... - MF 11:29 AM Software Development: RE: DSP Hello World won't link
- I had originally downloaded Aug-2012 SDK (angstrom-eglibc-i686-armv5te-toolchain-qte-v2012.05.tar.bz2)and installed this using the following command:
sudo tar xjvf angstrom-eglibc-i686-armv5te-toolchain-qte-v2012.05.tar.bz2 -C /
th...
10/03/2012
- GG 02:46 PM Software Development: RE: DSP Hello World won't link
- Hi Mary,
In regards to your first issue, the fix you made is correct. The arm_main.cpp file is simply out of date and needs to be updated. I will look into that.
As far as your linking issue, it looks like you are using the toolc... - I am following the instruction for the DSP Hello Word project wiki page.
First Problem:
I got a compile error for this line:
lpMessageOutbound->SendMessage(lpMessageBuffer, strlen(lpMessageBuffer)+1);
saying that there was no... - KV 01:04 PM Software Development: RE: mitydsp L138 starter file
- Dominic,
Download of the starter file is succussful.Unzip is failing. attached is the screenshot of the message. Winzip works withw the gel file you sent me.
10/02/2012
- DG 10:41 PM Software Development: RE: mitydsp L138 starter file
- Sorry you seem to be having issues downloading the file. I tried here and was able to download the file and extract it successfully - probably an error occurred during your download. The copy you attached to your post was only 235.1 KB, ...
- Downloaded http://support.criticallink.com/redmine/attachments/1659/CL_MityDSPL138_StarterWare_06_20_12.zip
unable to unzip the file. Winzip complains that it is not a valid archive file.
I am looking for a valid gel or ccxml file fo... - MW 12:57 PM PCB Development: RE: SPI1_SCS0 -> Edgeconnector pin 53?
- Yes,
However, this pin should normally be treated as RESERVED as it is the chip select line for the on-board SPI NOR FLASH. The NOR FLASH is used as the primary first and second stage boot loader media by the OMAP-L138.
This pin w... - Hi,
is the pin 53 on the edgeconnector (L138-Module) connected with the E19-pin (SPI1_SCS[0]) on the OMAP processor?
thanks,
Christian
09/27/2012
- AB 04:04 PM PCB Development: RE: MMCSD
- Conor,
We have addressed the MMC issues in the datasheet which can be found here by selecting the latest board version: http://support.criticallink.com/redmine/projects/indio/wiki/Industrial_IO_Revision_Information
During the revie... - CO 06:20 AM PCB Development: RE: MMCSD
- Thanks Mike. Once I saw it, I realised the reason why - that stubs on the connector line would warrant concern. Plus when you sent me the link to the versioning page on another posting, I noted the red Xs over the MMCSD0 pins but I faile...
- MW 05:36 AM PCB Development: RE: MMCSD
- Hi Conor,
You're right. I am trying to figure out what happened here and I see a note in a review that there was concern (not confirmed, mind you) about leaving stubs on the MMC signal path by running the nets to both the SD Card con... - CO 04:24 AM PCB Development: RE: MMCSD
- None of the documented MMCSD0 connections on the J700 are wired up. Be nice if that was documented.
- EB 09:47 AM PCB Development: RE: Intermittent boot failure w/ U-boot
- I found the problem.
It was not seating well in the SODIMM socket.
That's a long story, but was my fault.
I am curious though, about which pins would cause that.
Thanks,
Emmett - EB 09:14 AM PCB Development: RE: Intermittent boot failure w/ U-boot
- Here's the SOM sheet, which I believe has everything pertinent to this issue.
U1 is providing a 67ms delay which I'm sure is overkill, but should work OK.
I get the same result w/ power-up or with the reset switch SW1 @ U1.
Also - w...
09/26/2012
- MW 06:18 PM PCB Development: RE: Intermittent boot failure w/ U-boot
- What do you have for a reset circuit? How is the reset input driven?
U-Boot shouldn't hang if there is no RS-232 activity (doesn't look at flow control or anything). I don't think it uses any kind of BAUD detect either.
-Mike - I have the 1808F on our carrier board now.
It is working and communicating RS232.
About 3/4 of power-on events, it locks up.
There is no RS232 comm, and the FPGA never finishes configuration.
The same SOM on the Industrial I/O boar... - CO 12:05 PM PCB Development: RE: MMCSD
- Hi Critical Link engineers:
If I probe (carefully) pin 5 of an SD card in place, I see the SDIO Clock. My scope says it's 37.5MHz and 3.5V roughly.
According to the datasheet if I then hook up a probe to J700, pin 23 on the Industr...
09/25/2012
- CO 11:49 AM PCB Development: RE: MMCSD
- Further to this - I have my WL1271 module hooked up to the MityDSP board. However the driver just powers up and down and up and... It successfully toggles GPIO0/5 each time (it's not 7 as documented in MityDSP baseboard docs). I took the...
09/18/2012
- MW 05:42 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- See Table 1 in the "datasheet":http://www.mitydsp.com/images/upload/File/MityDSP-L138F%20Spec.pdf. The pins are tagged with an asterix and a note at the bottom of the table. But yes, those are the 8 pins.
-Mike
- MM 12:10 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Mike,
I didn't realize that the DVI wouldn't work with the LX-45, luckly we don't need the DVI interface. For reference are the 8 pins missing for DVI the only pin difference between LX16 and LX45?
Thanks,
Matt - CO 10:18 AM Software Development: RE: Simple GPIO toggle
- It works! Thanks for all your help on this Mike. I really appreciate that.
Big Note: It still does not work on Gpio0/7. Because gpio0/7 is not actually routed to the J700 connector!!!
Look at the links for the latest rev of the boa... - CO 08:56 AM Software Development: RE: Simple GPIO toggle
- My board is rev: 80-000268RI-2B, the latest revision.
Ah yes. I see. I really should have spotted it myself as I went and checked GP0[7] in the L138 docs and saw that it was multiplexed with PWM and mcASP functionality. But as GP0[6] ... - MW 07:21 AM Software Development: RE: Simple GPIO toggle
- Hi Conor,
Think I found it. If you check the schematics from this "page":http://support.criticallink.com/redmine/projects/indio/wiki/Industrial_IO_Revision_Information, it looks like GP0_7 is pin-muxed for the AXR15 (done in the base... - CO 05:56 AM Software Development: RE: Simple GPIO toggle
- I took the MDK from 2012-03-12 and compiled uBoot and uImage from defaults (using industrialio-defconfig for the kernel). I then flashed those to the board and it booted up just fine. But GPIO0/7 will still not toggle. It will change gpi...
- CO 03:51 AM Software Development: RE: Simple GPIO toggle
- I cannot find any particular reason for the pins to do this in the code. I'll recompile the kernel and uboot on the off chance something is happening there... I never updated uboot and I believe some gpio pin parameters are set there too.
09/17/2012
- MW 07:29 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Matt,
Are you sure you have an LX-45 based FPGA? The LX-45 does not bond out 8 pins that the LX-16 does. These include pins F12, E12, D12, C12, F11, E11, E7, and E8 (this should be documented in the specification). All of this sign... - MW 07:09 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Matt,
Are you using a wide screen monitor? We've seen some widescreen monitors won't lock up with VGA resolution due to the aspect ratio. You might try using the wvga_800x480 setting instead (that is the resolution that the visio... - MM 06:32 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Mike,
Yes, I am using the DVI connector. The FPGA image I am using is one I generated for the x45 FPGA from the source code in examples/industrial_io/fpga. I though this code was for the vision framework kit and would have support ... - MW 05:58 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Matt,
If you are trying to use the DVI connector, you need to use the FPGA image that was built to run with the DVI interface and not the LCD interface. The builds are different as the clock rates and pin-outs/routing are not the ... - MM 05:42 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Ok good news! I got the FPGA bin files needed so that the FPGA ready light comes on. The not so great news is I can't get anything to show up on the monitor connected to the industrial_io board.
I'm following the instructions from:
... - MM 10:11 AM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Mike,
Last week I didn't really have time to work on it, this week I'll know if I need more assistance.
-Matt - CO 08:46 AM Software Development: RE: Simple GPIO toggle
- That's supposed to be GPIO0/6 by the way...
- CO 08:44 AM Software Development: RE: Simple GPIO toggle
- Certainly... The PCB number is "120540". I've no boards plugged in at all - just the L138 module and the baseboard. There's only a single wire pushed into the connector which is connected to a voltmeter.
I'll try another one.....
O... - MW 08:39 AM Software Development: RE: Simple GPIO toggle
- Hmmm...
Do you have an expansion board plugged in right now? Can you disconnect it if you do?
It's possible that the outputs might not match the inputs if there is an external driver or short that is stronger than the driver in th... - CO 08:29 AM Software Development: RE: Simple GPIO toggle
- GPIO0/15 is the opposite which is rather odd. It starts out as 0, whereas GPIO0/7 starts out as 1:
root@mityomapl138:/sys/class/gpio# cat gpio15/value
0
root@mityomapl138:/sys/class/gpio# echo "out" > gpio15/direction
root@mityomap... - CO 08:21 AM Software Development: RE: Simple GPIO toggle
- Thanks Mike,
When I cat from /sys/class/gpio7/value, it reads "1" all the time, no matter what I've previously written. I did think that I was reading from the wrong pin so I had checked that...
The board is a L138F in an Industria... - MW 07:23 AM Software Development: RE: Simple GPIO toggle
- Hi Conor,
I don't see anything wrong with your approach. You might check the value that the pin is reading back (e.g., cat /sys/class/gpio7/value). If the pin is stuck, it should right a "1" in all cases. If it is toggling, then per... - I see this has been asked before in various ways so sorry to ask again (I'm not getting it!).
I have pin 19 from J700 hooked up to a meter. The MityDSP docs say this is GPIO, bank 0 offset 7.
So I should be able to toggle the pin b...
09/16/2012
- Like to seek your help on an uPP related question. I plan to burst out I and Q data from memory using the two uPP channels to the FPGA. In fact, I plan to drain most of the 256MB RAM using multiple DMA calls (if required). I see from ...
09/15/2012
- MW 06:56 AM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Matt,
Did you get through this, do you still need assistance?
-Mike
09/14/2012
- FT 06:24 PM Software Development: RE: Problem with uPP in DLB
- Greg,
Thanks for answer.
By the way, do you have a dummy FPGA load (in .bin format) that output "known fake data" on uPP?
It can be very very very useful.
Thanks!
-François - GG 05:15 PM Software Development: RE: Problem with uPP in DLB
- François,
Glad to hear that fixed your problem!
In regards to your follow up question, yes, you will most likely need to invalidate the cache on your receive buffer each time before passing it into the DspUpp receive function in ...
09/13/2012
- FT 02:43 PM Software Development: RE: Problem with uPP in DLB
- Greg,
You was right on and you make my day!
Now, I have another question regarding the cache. I used the uPP in DLP mode for uPP driver integration. However, it is a temporary solution because our FPGA is not yet ready. When our FP... - GG 02:24 PM Software Development: RE: Problem with uPP in DLB
- Hi François,
We have not done any work with running the system in digital loopback mode. The fact that you are getting a response back and not just hanging on the receive mailbox is a good sign. The pinmuxing should not matter as dig... - I am trying to use uPP in DLP mode with an MityDSP1810F board but my rx buffer is still empty after a "ransaction.
I am using modified version of DspUpp.cpp file.
Here code snipped
*buffer.c*
09/12/2012
- We are using uPP in our design - UPP XDx signals & BOOT function are muxed, what must I do?
- I am actually design an eval board using your L138 module. I am wondering if I need to care about the BOOT pins (muxed with others fonctionalities), so that your L138 module will properly boot, or is that done within your L138 module.
D...
09/11/2012
- We need to switch power off to the entire card based on USB activity.
Any easy way to do this?
Also how long is the boot time to load the OMAP code and FPGA code from NVRAM from power up to being able accept commands from the USB? - MW 03:27 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- It's the same thing. It got branded with two names early on. Profibus really only works with the MityARM-1810, as there is a licensing restriction on the PRU microcode that runs the profibus stack. You can evaluate it using the other ...
- MM 02:38 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- I guess now is a good time to ask, I'm not sure industrial I/O devkit or the PROFIBUS Development Kit, or if there is even a difference between to two. This question came up before and I guess we might as well just ask the expert.
Th... - MW 12:07 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Matt,
All of the images on the example site are for an LX16, which (I thought) was the standard size FPGA for modules delivered with the Industrial I/O DevKit boards. The images for the LCD on the wiki page are for LX16 based modu... - MM 11:56 AM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- *Edit*
The board acually says REV A, not sure if it matters. - MM 11:52 AM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Ok, thanks Mike. I'll be sure to check out the newer branches. I was able to get fpga_ctrl to load using the uimage from the MDK folder.
I had a few more questions about getting the screen to work.
I can't seem to be able to get th... - MW 07:23 AM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Matt,
There are several branches on our git server. The "master" is somewhat older, which is your 2.6.34-rc1. The newer MDKs use different branches. Most use the mitydsp-linux-v3.2 branch. You can check that version of the kern... - MW 02:00 PM PCB Development: RE: Usage of GP0 pins on MityDSP-L138F (Posted on behalf of a Customer)
- The "datasheet":http://www.mitydsp.com/images/upload/File/MityDSP-L138F%20Spec.pdf for the MityDSP-L138F contains this information. Perhaps it is not clear?
Table 1 in the datasheet lists for Pin-Out for the SOM. For the pins labell... - My programmers need to know:
What (if anything) is connected to the GPIO pins on port GP0 onboard the MityDSP-L138F board.
What we want to hear is that the CPU GPIO pins are wired only to the pins of the 200-pin SODIMM connecter, and...
09/10/2012
- MM 10:05 AM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Mike,
If I understand what I am doing correctly, I am using version 2.6.34-rc1 and I got the kernal from git://support.criticallink.com/home/git/linux-davinci.git.
Thanks,
Matt
09/07/2012
- MW 06:40 PM Software Development: RE: Requirements to install the fpga_ctrl.ko?
- Hi Matt,
The error messages you are getting are from the kernel module files not being compiled against the same version of the kernel. Newer filesystems have udpated kernel module files (the ones on the wiki are admittedly pretty ol... - Hi,
I've been working with our MityDSP L138F and devolopment board for a few days, today I tried to follow the insturctions to configure the LCD (http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/LCD_configuration)
... - SW 09:49 AM Software Development: RE: kernel build
- duh, I guess it helps to execute the instructions you guys post. After tftp'ing the new kernel I would just type boot at the prompt and then boot up the kernel in flash. I was able to get the new kernel to boot this morning. sorry abo...
09/06/2012
- TC 05:59 PM Software Development: RE: kernel build
- Scott may have found the issue ... he is going to verify and re-post ...
- Hello, I am trying to build the kernel to support EXT4 filesystems. I have downloaded the latest configuration MDK_2012-08-10. I run the menu config with the default config file. The menuconfig displays Linux/arm 3.2.0 Kernel configur...