Activity
From 12/04/2012 to 01/02/2013
01/02/2013
- 09:01 AM PCB Development: RE: SATA board connector
- Alex,
I haven't had the opportunity to get a SATA connector for our board. That is the one I was looking at. I lik...
12/31/2012
- 10:17 AM PCB Development: RE: Used EMIFA-Signals/Pins
- That's great Mike - exactly what I hoped to hear :)
I was wondering if you had done precisely this given that the ... - 08:10 AM PCB Development: RE: Used EMIFA-Signals/Pins
- Hi Conor,
On the Non-FPGA modules, all 4 of these signals have a 1K Ohm series resistor between the on-board nets ... - 07:49 AM PCB Development: RE: Used EMIFA-Signals/Pins
- In the case of the Industrial IO board though, pins 197 through 200 are tied directly to 3.3V for the VCCO_[0,1] bank...
12/27/2012
- 01:51 PM Software Development: RE: Debugging DSP in VirtualBox?
- Do you know of any emulators that are useable from within the current Oracle VirtualBox or is there a work around? I...
12/26/2012
- 03:55 PM Software Development: RE: SYSBIOS & Starterware
- Hi Jean-Baptiste -
It would be my understanding that if you are going to use SYS/BIOS that you should start with ...
12/23/2012
- 09:36 PM Software Development: RE: after update the root-FS and Kernel NFS errors appear at startup
- The most recent filesystem involved transitioning from Anstrom 2008 to Angstrom 2012.05, which also migrated from the...
- 10:48 AM Software Development: RE: after update the root-FS and Kernel NFS errors appear at startup
- To give you more inforamtion about the startup sequence I add the whole log-file of it.
Can it be that there is so... - Hi,
I updated the Root-File-System on my module with the Base-FS out of the latest MDK (2012-08-10). I copied also... - 09:28 PM Software Development: RE: DSP Link example not working
- Ok,
I will post to your other topic for enabling the network on the newer MDK.
Are you building the example sof... - 03:04 PM Software Development: RE: DSP Link example not working
- Mike,
sorry for my really late response....
I was using the factory installed filesystem with the associated ke...
12/22/2012
- 07:24 PM Software Development: RE: u-Boot configuration for DSP-Startup
- Christian
this page
http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Quick_Start
should ... - 07:19 PM Software Development: RE: u-Boot configuration for DSP-Startup
- Thank you Tom for your quick answer!
For the moment I have a DSP-only setup but later I want to use both: Linux an... - 07:11 PM Software Development: RE: u-Boot configuration for DSP-Startup
- Christian
You can store the DSP image in flash. I am assuming you are running a DSP-only setup (i.e. no linux system... - Hi,
At the moment I'm at a point where I don't know how...
I have a DSP-image and want to load it at the startu...
12/20/2012
- 09:49 PM FPGA Development: RE: Pinout on L138-FG-225-RC
- Michele,
In response to your GPIO bank question:
Yes you can use a single core in the FPGA and have it utilize ... - 09:44 PM PCB Development: RE: SATA board connector
- Scott,
Just wondering if you found a drop in replacement. We actually just tried doing this on an in-house test fi... - 09:39 PM Software Development: RE: tftp access violation
- Wade,
I'm going to take a stab in the dark here on a suggestion to give you something to try. If you think you may... - 09:26 PM Software Development: RE: The Jtag Interface
- If you can wait approximately a week or two Digikey should have them in stock for ordering (http://www.digikey.com/pr...
- 08:33 PM Software Development: RE: The Jtag Interface
- hi mike
I buy a 1808-FX-225-RC. it is without the adapter board. How can I get one？
thanks - 09:49 AM Software Development: RE: New UBoot Image That Fixes Bootelf Hang When Running Starterware
- Sorry for the delay.
The code to support the updated features was checked into our "git server":http://support.cri... - 09:34 AM Software Development: RE: New UBoot Image That Fixes Bootelf Hang When Running Starterware
- Was there an official release?
What / where is the latest/greatest? - 09:41 AM Software Development: RE: PROC_read()
- Or.... you can use PROC_read, but you need to build your own synchronization hooks. This is what Greg was alluding t...
- 09:40 AM Software Development: RE: PROC_read()
- The PROC_read() API is not guarded. It's effectively a memory copy (dealing with the VM addressing under linux).
... - 09:21 AM Software Development: RE: PROC_read()
- Greg,
Can you clarify your answer with a bit more detail? Are you saying that the DSP should send a message to the...
12/19/2012
- 02:54 PM Software Development: RE: PROC_read()
- Hi Terrence,
What I've seen done here in situations like you are describing is to use the dsplink interfaces and ... - 02:45 PM Software Development: RE: PROC_read()
- To clarify. I am using Critical Link's API MityDSP::tcDspApp to load the DSP application, configure the shared memor...
- I have a shared memory read issue between the ARM and DSP processor that I am trying to resolve. I am using PROC_rea...
12/18/2012
- 09:38 AM FPGA Development: RE: I2C issues on SLX45
- Further - I broke my OLED writes into < 32 bytes each and retested. That works fine and if it was unreliable, the pic...
- 08:54 AM FPGA Development: RE: I2C issues on SLX45
- Hi guys. Got a chance to test this today. That's a lot better! The i2cdetect scan picks up the device and shows "--" ...
- 09:00 AM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- The EMIFA DCM may not be required. If you do not require any other clocks than the 100 MHz (when running at 300 MHz ...
- 08:32 AM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- Hmmm. Not sure now because I'm afraid I didn't use the DCM at all! I didn't connect the i_ema_clk directly but via a ...
- 08:13 AM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- Dear Conor,
I appreciate your help!
I have the suspect that the component emaclkdcm-Emifa_dcm is a digital cloc... - 05:43 AM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- The learning curve for Xilinx tools is pretty darn steep anyway without jumping in at the deep end!
What *I* did i...
12/17/2012
- Hello,
I'm working to a project with a MityOMAP-L138-FX-225-RC.
Currently, I try to use SYSBIOS into this module... - 01:44 PM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- Dear Jean-Pierre,
I am a newbie too in fpga programming: could you please post me a suggestion about the solution?
... - 10:20 AM FPGA Development: RE: I2C issues on SLX45
- Scratch that - I see -DDEBUG is in the Makefile :)
- 10:17 AM FPGA Development: RE: I2C issues on SLX45
- No worries Mike. I used to be a QA guy so I must have a knack for finding these things! Like communicating with a non...
- 09:17 AM FPGA Development: RE: I2C issues on SLX45
- Hi Conor,
I am updateing (via editing) the patch on the previous post. We've finished some testing here and found...
12/16/2012
- 09:04 AM FPGA Development: RE: I2C issues on SLX45
- Thanks Mike, I looked at the driver code but wasn't really familiar enough with it to help. I was suspicious somethin...
12/14/2012
- 01:46 PM FPGA Development: RE: I2C issues on SLX45
- Hi Connor.
I think we may have found the issue. There may be a bug in the linux driver.
If you are OK recompil...
12/11/2012
- 08:40 AM Software Development: RE: dsplinkk.ko compatibility
- I updated my instructions to clarify the commands on the last post...
-Mike
- 08:34 AM Software Development: RE: dsplinkk.ko compatibility
- If you added or removed features from the kernel, you may need to rebuild the dsplink drivers.
To do that:
# s... - 08:09 AM Software Development: RE: dsplinkk.ko compatibility
- Michael Williamson wrote:
> There should be a dsplinkk.ko file in the /lib/modules/3.2.0/ directory in the reference...
12/06/2012
- 01:51 PM Software Development: RE: Linux DaVinci Video Port Interface (VPIF)
- My OMAP-L138 VPIF issue has been resolved! There was a conflict with PINMUX16 and PINMUX17 control register settings...
- 12:25 PM Software Development: RE: Extremely slow root file system
- Thanks Mike for answer.
I forwarded your last comment to our HW engineer.
Chances are I will not get other que... - 09:23 AM Software Development: RE: Extremely slow root file system
- The approach by your HW designer is fine.
Tri-stating the unused lines that are connected to the EMIFA and IRQ l... - 09:13 AM Software Development: RE: Extremely slow root file system
- Mike,
The unused I/O pins in our FPGA design seems to be the culprit.
Here a comment from our hardware engineer...
12/05/2012
- 03:22 PM Software Development: RE: Extremely slow root file system
- Please make sure that any unused IO pins on your FPGA design are "floating" and not "pulled-down" in the bitstream ge...
- Hardware configuration: Industrial IO board + L138-DI-225-RI
We have a FPGA application that transmit data to DSP ... - 10:49 AM FPGA Development: RE: I2C issues on SLX45
- I dropped the drive strength to 6 on the SCL and SDA lines and it makes a slight difference - not so much ground boun...
- 07:20 AM FPGA Development: RE: I2C issues on SLX45
- (Busy writing reports instead of doing the work the reports are about!)
For drive strength I was using the Xilinx ...
12/04/2012
- 11:29 AM Software Development: RE: Linux DaVinci Video Port Interface (VPIF)
- Hi Terrence,
Sorry for the confusion. The linux kernels 2.6.X tracked TI's Platform Support Package releases from... - 09:55 AM Software Development: RE: Linux DaVinci Video Port Interface (VPIF)
- I am currently using MDK_2011-12-05 DaVinici Linux kernel to support VPIF on a OMAP-L138F SoM platform. I attempted ...
- I need to setup a VPIF interface (ala V4L2) using a Mity OMAP-L138F SoM platform running DaVinci Linux to support, BT...
- 07:12 AM FPGA Development: RE: I2C issues on SLX45
- Hi Conor,
What are you using for drive strength on the FPGA? You might be able to lower the drive strength if the... - 05:50 AM FPGA Development: RE: I2C issues on SLX45
- Hi again. It looks like the fpga is doing the right thing but the rise times are just too slow. Er. I guess that's my...
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