Activity
From 12/16/2012 to 01/14/2013
01/14/2013
- CR 03:46 PM FPGA Development: RE: Creating FPGA Base-Project - core manager problem
- Hi Greg,
i opend the "build_lcd_rev_c" example project and migrate it to the 14.4 version. I think the migrtion works but there are some files needed what i can't find in the MDK.
see the attached picture. Therfore i couldn't try to ...
01/13/2013
- DG 09:39 PM Software Development: RE: Debugging DSP in VirtualBox?
- I have being using SD XDS510 USB + VirtualBox 4.1.16 + CCS 5.2.0 with no problems.
- GG 05:07 PM FPGA Development: RE: Creating FPGA Base-Project - core manager problem
- Hi Christian,
The ISE Webpack license should be sufficient for what you are trying to do.
Try opening one of the projects in MDK\examples\industrial_io\fpga\build_* and see what that tells you. You will most likely be asked to mi...
01/12/2013
- Hi,
I've started with the FPGA-design in ISE Webpack 14.4.
I added all files from "MDK_2012-08-10\fpga\vhdl" to the project and also the "EMIFA_dcm.xco" file. I tried to regenerate this core in my project but I don't know why, but i... - CR 02:11 PM Software Development: RE: DSP Link example not working
- Mike,
I got it and it's working now :)
Thanks.
Christian - CR 02:10 PM Software Development: RE: u-Boot configuration for DSP-Startup
- Tim,
It's working now.
Thanks!
Christian
01/10/2013
- MW 12:18 PM Software Development: RE: PRU Kernel Driver
- The PRU drivers are not installed. You'll need to rebuild the kernel. You may need to patch in the PRU drivers as well.
-Mike
- Do any of the kernels built by critical link have the PRU drivers installed? Or do I have to rebuild a kernel with this driver?
Jeremy - MW 08:14 AM Software Development: RE: AM1808-industrilal I/O performance
- Oh. You should be all set, see [[Setting_CPU_Speed]].
-Mike
- ML 08:11 AM Software Development: RE: AM1808-industrilal I/O performance
- Hi,
Yes - both kernel settings is set to 'y'.
root@vdr:/sys/devices/system/cpu/cpu0/cpufreq# cat scaling_available_frequencies
456000 408000 372000 300000 200000 96000
Mads-l
- MW 07:58 AM Software Development: RE: AM1808-industrilal I/O performance
- Can you check if CONFIG_CPU_FREQ=y is set in the 3.1 kernel configuration. Also can you confirm that the CONFIG_CPU_FREQ_GOV_USERSPACE=y?
can you also: - ML 02:24 AM Software Development: RE: AM1808-industrilal I/O performance
- Hi,
I am usually running the 3.1.x kernel that I build from the git repository downloaded from Critical link. Here are kernel logs for both this kernel and the kernel which resides in SPI-flash from factory.
I notice that the /sys/ke...
01/09/2013
- MC 11:38 AM FPGA Development: RE: FPGA GPIO: toggle problem
- Dear all,
by the way, Greg was right saying that the GPIO core configuration I posted the first time could work (IndustrialIO_top file; a day ago): today I tried to reflash that file on fpga, and monitoring the outputs on the back con... - MW 10:07 AM FPGA Development: RE: FPGA GPIO: toggle problem
- ON the bitfile generation, please make sure that your unused IOBs are "floating" and not pulled down or up.
-Mike
- GG 09:58 AM FPGA Development: RE: FPGA GPIO: toggle problem
- Hi Michele,
The only time I've experienced the board reseting due to an FPGA load is when I was mistakenly loading the wrong file (i.e. I tried to cat the .bit file instead of the .bin...). If you take the file you sent me and switch ... - MC 05:25 AM FPGA Development: RE: FPGA GPIO: toggle problem
- Hi Greg,
thank you for the hint and the fast answer!
Now I have another problem: I modified the GPIO instantiation as you suggested, following the wiki link you submit: in particular I followed the "GPIOs as Outputs" template.
I suc... - MW 09:06 AM Software Development: RE: AM1808-industrilal I/O performance
- What version of the kernel are you using? The pre-programmed one on FLASH? That version of the kernel may be older than the patch that adds support for upping the speed beyond 300 MHz.
Can you do a "dmesg" and dump the log file?
... - ML 08:03 AM Software Development: RE: AM1808-industrilal I/O performance
- This is the "factoryconfig" printout:
U-Boot > factoryconfig
Factory Configuration:
Config Version : 1.1
MAC Address : 00:50:C2:BF:8B:D2
Serial Number : 110009
FPGA Type : 0 [none]
Part Number : 1808-FX-225-RC
U-Boo...
01/08/2013
- GG 12:54 PM FPGA Development: RE: FPGA GPIO: toggle problem
- Hi Michele,
The reason that you're not seeing the echo'ed value of the GPIO change is due to the way the core is connected. In order to solve this you will need to connect the o_io outputs of the GPIO core back to i_io. This was most ... - MC 09:53 AM FPGA Development: RE: FPGA GPIO: toggle problem
- Sure Greg, thanks for the help!
The name is IndustrialIO_top, because I worked on it from your file..
- GG 08:59 AM FPGA Development: RE: FPGA GPIO: toggle problem
- Hi Michele,
Could you post your VHDL instantiation of the GPIO core? Perhaps some of settings or ports were set incorrectly...
Thanks,
\Greg - Dear All,
after I successfully created a GPIO core on the FPGA framework, burnt onto the FPGA, successfully enumerated the FPGA cores and installed the fpga_gpio kernel object, I was trying to toggle a GPIO pin on FPGA using userspace... - MW 09:48 AM Software Development: RE: AM1808-industrilal I/O performance
- In u-boot, run the command "factoryconfig".
-Mike
- ML 09:31 AM Software Development: RE: AM1808-industrilal I/O performance
- Here is some information - cannot get any useful information from the bootlog.
*From Bootloader startup:*
Jumping to entry point at 0xC1080000.
U-Boot 2009.11 (Mar 31 2011 - 19:39:18)
I2C: ready
DRAM: 128 MB
NAND: 256 MiB
...
01/07/2013
- MF 12:38 PM Software Development: RE: MSGQ access
- The answer was in the Makefile. I had to add in all the defines.
DEFINES=-DTRACE_ENABLE \
-DOS_LINUX \
-DMAX_DSPS=1 \
-DMAX_PROCESSORS=2 \
-DID_GPP=1 \
-DPROC_COMPONENT \
-DPOOL_COMPONENT \
-DNOTIFY_COMPONENT \
-DMPCS... - GG 09:20 AM Software Development: RE: MSGQ access
- Hi Mary,
I think the reason you're getting a compiler error is because you're only including a single file from the DSPLink code. Take a look at the Makefile used to create the libdsp libraries (MDK/sw/ARM/linux/libdsp/Makefile) for ...
01/04/2013
- Is there a way to use the MSGQ library? I would like to call MSGQ_locate() and MSGQ_close(). I have a project based on the HelloDSP example, but when debugging if I stop before the application ends, I get an error opening the message qu...
- MW 10:43 AM Software Development: RE: AM1808-industrilal I/O performance
- Hi Mads-l,
Can you print out the factory configuration information? Certain modules (Revision "A" silicon, IT silicon and lower speed grade options) do not support frequencies above 300 MHz (rev A silicon, 375 for IT silicon) and the... - I am currently testing network performance. Having installed the netperf utility in my root file system, I am able to test performance between my development machine and the Industrial i/O card.
Running netperf, measuring network thr...
01/03/2013
- Has there been any work done regarding a Profibus master on the MityArm AM1810?
01/02/2013
- SW 09:01 AM PCB Development: RE: SATA board connector
- Alex,
I haven't had the opportunity to get a SATA connector for our board. That is the one I was looking at. I like to hear you were able to get it flush on the board. I will look into getting some and trying it out. Thanks, Scott
12/31/2012
- CO 10:17 AM PCB Development: RE: Used EMIFA-Signals/Pins
- That's great Mike - exactly what I hoped to hear :)
I was wondering if you had done precisely this given that the wiki said the non-FPGA modules would work. But I have an L138F here not an L138 so couldn't really check it myself and w... - MW 08:10 AM PCB Development: RE: Used EMIFA-Signals/Pins
- Hi Conor,
On the Non-FPGA modules, all 4 of these signals have a 1K Ohm series resistor between the on-board nets and the edge connector. This effectively makes putting a non FPGA module into a board like the Industrial I/O kit OK if... - CO 07:49 AM PCB Development: RE: Used EMIFA-Signals/Pins
- In the case of the Industrial IO board though, pins 197 through 200 are tied directly to 3.3V for the VCCO_[0,1] bank connections to the FPGA. These correspond to:
12/27/2012
- JS 01:51 PM Software Development: RE: Debugging DSP in VirtualBox?
- Do you know of any emulators that are useable from within the current Oracle VirtualBox or is there a work around? It would be nice to use the same Virtual Box to develop for both the DSP and ARM.
12/26/2012
- TC 03:55 PM Software Development: RE: SYSBIOS & Starterware
- Hi Jean-Baptiste -
It would be my understanding that if you are going to use SYS/BIOS that you should start with a sys/bios project. Likely sys/bios needs to be initialized, etc. So, simply starting with starterware and adding a sys/...
12/23/2012
- MW 09:36 PM Software Development: RE: after update the root-FS and Kernel NFS errors appear at startup
- The most recent filesystem involved transitioning from Anstrom 2008 to Angstrom 2012.05, which also migrated from the well understood SysVinit scripts to systemd. When we built up the reference filesystems, we failed to enable the netwo...
- CR 10:48 AM Software Development: RE: after update the root-FS and Kernel NFS errors appear at startup
- To give you more inforamtion about the startup sequence I add the whole log-file of it.
Can it be that there is something wrong with the delivered kernel-image in the MDK? Maybe the networkconfiguration..... - Hi,
I updated the Root-File-System on my module with the Base-FS out of the latest MDK (2012-08-10). I copied also the kernel from the new MDK\images on the modul.
Now I get the following Errors during the startup sequence:
- Fail... - MW 09:28 PM Software Development: RE: DSP Link example not working
- Ok,
I will post to your other topic for enabling the network on the newer MDK.
Are you building the example software or using precompiled binary images from our wiki?
For this error, the main issue is that the newer filesystems ... - CR 03:04 PM Software Development: RE: DSP Link example not working
- Mike,
sorry for my really late response....
I was using the factory installed filesystem with the associated kernel. Then i installed the newest base-filesystem with the kernel from MDK 2012-08 on my module. But after installation ...
12/22/2012
- TI 07:24 PM Software Development: RE: u-Boot configuration for DSP-Startup
- Christian
this page
http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Quick_Start
should explain it.
cheers
/Tim
- CR 07:19 PM Software Development: RE: u-Boot configuration for DSP-Startup
- Thank you Tom for your quick answer!
For the moment I have a DSP-only setup but later I want to use both: Linux and my DSP-application.
Can you explain me also how I can startup both?
Christian - TI 07:11 PM Software Development: RE: u-Boot configuration for DSP-Startup
- Christian
You can store the DSP image in flash. I am assuming you are running a DSP-only setup (i.e. no linux system running).
To change the boot command you stop the u-boot process (press enter before the count-down ends) and edit the... - Hi,
At the moment I'm at a point where I don't know how...
I have a DSP-image and want to load it at the startup. I red in the u-Boot wiki that there is a special command bootdsp available for this.
But my first question about t...
12/20/2012
- AB 09:49 PM FPGA Development: RE: Pinout on L138-FG-225-RC
- Michele,
In response to your GPIO bank question:
Yes you can use a single core in the FPGA and have it utilize pins from both banks (I have done it in a couple of my designs and have had no issues).
Alex - AB 09:44 PM PCB Development: RE: SATA board connector
- Scott,
Just wondering if you found a drop in replacement. We actually just tried doing this on an in-house test fixture here and I selected a Molex 19103 which is pin-compatible however the footprint isn't quite right and the pins had... - AB 09:39 PM Software Development: RE: tftp access violation
- Wade,
I'm going to take a stab in the dark here on a suggestion to give you something to try. If you think you may have overwritten some important memory areas than it may be advised to reflash the board with the UBoot image that is p... - AB 09:26 PM Software Development: RE: The Jtag Interface
- If you can wait approximately a week or two Digikey should have them in stock for ordering (http://www.digikey.com/product-search/en?x=0&y=0&KeyWords=80-000286).
Otherwise please send an e-mail to info@criticallink.com citing this pos... - YW 08:33 PM Software Development: RE: The Jtag Interface
- hi mike
I buy a 1808-FX-225-RC. it is without the adapter board. How can I get one？
thanks - MW 09:49 AM Software Development: RE: New UBoot Image That Fixes Bootelf Hang When Running Starterware
- Sorry for the delay.
The code to support the updated features was checked into our "git server":http://support.criticallink.com/gitweb/?p=u-boot-mitydspl138.git;a=summary, but we have not changed our factory configuration image config... - EB 09:34 AM Software Development: RE: New UBoot Image That Fixes Bootelf Hang When Running Starterware
- Was there an official release?
What / where is the latest/greatest? - MW 09:41 AM Software Development: RE: PROC_read()
- Or.... you can use PROC_read, but you need to build your own synchronization hooks. This is what Greg was alluding to - we used a simple MSGQ message to pass pointers to buffers between the two processors. It was a bit hokey, but worke...
- MW 09:40 AM Software Development: RE: PROC_read()
- The PROC_read() API is not guarded. It's effectively a memory copy (dealing with the VM addressing under linux).
For guarded transfers or synchronized transfers, you need to use some of the other DSPLINK framework APIs, such as MSGQ'... - WC 09:21 AM Software Development: RE: PROC_read()
- Greg,
Can you clarify your answer with a bit more detail? Are you saying that the DSP should send a message to the ARM via IPC to hold off on accessing shared memory then send a follow-up message to indicate accessing memory is subseq...
12/19/2012
- GG 02:54 PM Software Development: RE: PROC_read()
- Hi Terrence,
What I've seen done here in situations like you are describing is to use the dsplink interfaces and send messages between the DSP and ARM to synchronize. In this way the DSP knows when it is safe to write and the ARM kno... - TL 02:45 PM Software Development: RE: PROC_read()
- To clarify. I am using Critical Link's API MityDSP::tcDspApp to load the DSP application, configure the shared memory region, and communicate with the DSP.
- I have a shared memory read issue between the ARM and DSP processor that I am trying to resolve. I am using PROC_read() function to copy data from DSP memory to a memory buffer used by the ARM. My question has to do with inter-processo...
12/18/2012
- CO 09:38 AM FPGA Development: RE: I2C issues on SLX45
- Further - I broke my OLED writes into < 32 bytes each and retested. That works fine and if it was unreliable, the pictures would show corruption which they don't. I can live with that! Thanks Mike.
I guess there two things for future ... - CO 08:54 AM FPGA Development: RE: I2C issues on SLX45
- Hi guys. Got a chance to test this today. That's a lot better! The i2cdetect scan picks up the device and shows "--" on non-existant devices just like it should. My i2ctemperature program reads out the ID and temperature properly now too...
- MW 09:00 AM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- The EMIFA DCM may not be required. If you do not require any other clocks than the 100 MHz (when running at 300 MHz CPU speed), then you can probably use a BUFG and skip the DCM.
The DCM does provide better skew management, but most ... - CO 08:32 AM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- Hmmm. Not sure now because I'm afraid I didn't use the DCM at all! I didn't connect the i_ema_clk directly but via a global net (a BUFG). This is what the Critical Link industrialio example does rather than use a DCM. Indeed, their examp...
- MC 08:13 AM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- Dear Conor,
I appreciate your help!
I have the suspect that the component emaclkdcm-Emifa_dcm is a digital clock manager of the emif clock, I'm not sure that I can eliminate it without pain.
Sure I will try not to include it in th... - CO 05:43 AM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- The learning curve for Xilinx tools is pretty darn steep anyway without jumping in at the deep end!
What *I* did is to add in the files I needed to my project starting with the top level VHDL file and the UCF file - I keep those in th...
12/17/2012
- Hello,
I'm working to a project with a MityOMAP-L138-FX-225-RC.
Currently, I try to use SYSBIOS into this module (ARM CPU part) with CCS environment.
I executed successfully some example (with task_delay) on the target using the ge... - MC 01:44 PM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- Dear Jean-Pierre,
I am a newbie too in fpga programming: could you please post me a suggestion about the solution?
I have the same inconvenience.:)
Thank you very much in advance!
Michele - CO 10:20 AM FPGA Development: RE: I2C issues on SLX45
- Scratch that - I see -DDEBUG is in the Makefile :)
- CO 10:17 AM FPGA Development: RE: I2C issues on SLX45
- No worries Mike. I used to be a QA guy so I must have a knack for finding these things! Like communicating with a non-existent device. I'd just finished doing the make so I made those changes and did make again. I'll add -DDEBUG in case ...
- MW 09:17 AM FPGA Development: RE: I2C issues on SLX45
- Hi Conor,
I am updateing (via editing) the patch on the previous post. We've finished some testing here and found a couple other bugs that should be cleaned up.
- Missed an additional read of that pesky done bit.
- Added a return...
12/16/2012
- CO 09:04 AM FPGA Development: RE: I2C issues on SLX45
- Thanks Mike, I looked at the driver code but wasn't really familiar enough with it to help. I was suspicious something was wrong codewise as the i2c driver was returning nonsense on the first read and then perfectly valid information on ...