Activity
From 11/24/2012 to 12/23/2012
12/23/2012
- MW 09:36 PM Software Development: RE: after update the root-FS and Kernel NFS errors appear at startup
- The most recent filesystem involved transitioning from Anstrom 2008 to Angstrom 2012.05, which also migrated from the well understood SysVinit scripts to systemd. When we built up the reference filesystems, we failed to enable the netwo...
- CR 10:48 AM Software Development: RE: after update the root-FS and Kernel NFS errors appear at startup
- To give you more inforamtion about the startup sequence I add the whole log-file of it.
Can it be that there is something wrong with the delivered kernel-image in the MDK? Maybe the networkconfiguration..... - Hi,
I updated the Root-File-System on my module with the Base-FS out of the latest MDK (2012-08-10). I copied also the kernel from the new MDK\images on the modul.
Now I get the following Errors during the startup sequence:
- Fail... - MW 09:28 PM Software Development: RE: DSP Link example not working
- Ok,
I will post to your other topic for enabling the network on the newer MDK.
Are you building the example software or using precompiled binary images from our wiki?
For this error, the main issue is that the newer filesystems ... - CR 03:04 PM Software Development: RE: DSP Link example not working
- Mike,
sorry for my really late response....
I was using the factory installed filesystem with the associated kernel. Then i installed the newest base-filesystem with the kernel from MDK 2012-08 on my module. But after installation ...
12/22/2012
- TI 07:24 PM Software Development: RE: u-Boot configuration for DSP-Startup
- Christian
this page
http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Quick_Start
should explain it.
cheers
/Tim
- CR 07:19 PM Software Development: RE: u-Boot configuration for DSP-Startup
- Thank you Tom for your quick answer!
For the moment I have a DSP-only setup but later I want to use both: Linux and my DSP-application.
Can you explain me also how I can startup both?
Christian - TI 07:11 PM Software Development: RE: u-Boot configuration for DSP-Startup
- Christian
You can store the DSP image in flash. I am assuming you are running a DSP-only setup (i.e. no linux system running).
To change the boot command you stop the u-boot process (press enter before the count-down ends) and edit the... - Hi,
At the moment I'm at a point where I don't know how...
I have a DSP-image and want to load it at the startup. I red in the u-Boot wiki that there is a special command bootdsp available for this.
But my first question about t...
12/20/2012
- AB 09:49 PM FPGA Development: RE: Pinout on L138-FG-225-RC
- Michele,
In response to your GPIO bank question:
Yes you can use a single core in the FPGA and have it utilize pins from both banks (I have done it in a couple of my designs and have had no issues).
Alex - AB 09:44 PM PCB Development: RE: SATA board connector
- Scott,
Just wondering if you found a drop in replacement. We actually just tried doing this on an in-house test fixture here and I selected a Molex 19103 which is pin-compatible however the footprint isn't quite right and the pins had... - AB 09:39 PM Software Development: RE: tftp access violation
- Wade,
I'm going to take a stab in the dark here on a suggestion to give you something to try. If you think you may have overwritten some important memory areas than it may be advised to reflash the board with the UBoot image that is p... - AB 09:26 PM Software Development: RE: The Jtag Interface
- If you can wait approximately a week or two Digikey should have them in stock for ordering (http://www.digikey.com/product-search/en?x=0&y=0&KeyWords=80-000286).
Otherwise please send an e-mail to info@criticallink.com citing this pos... - YW 08:33 PM Software Development: RE: The Jtag Interface
- hi mike
I buy a 1808-FX-225-RC. it is without the adapter board. How can I get one？
thanks - MW 09:49 AM Software Development: RE: New UBoot Image That Fixes Bootelf Hang When Running Starterware
- Sorry for the delay.
The code to support the updated features was checked into our "git server":http://support.criticallink.com/gitweb/?p=u-boot-mitydspl138.git;a=summary, but we have not changed our factory configuration image config... - EB 09:34 AM Software Development: RE: New UBoot Image That Fixes Bootelf Hang When Running Starterware
- Was there an official release?
What / where is the latest/greatest? - MW 09:41 AM Software Development: RE: PROC_read()
- Or.... you can use PROC_read, but you need to build your own synchronization hooks. This is what Greg was alluding to - we used a simple MSGQ message to pass pointers to buffers between the two processors. It was a bit hokey, but worke...
- MW 09:40 AM Software Development: RE: PROC_read()
- The PROC_read() API is not guarded. It's effectively a memory copy (dealing with the VM addressing under linux).
For guarded transfers or synchronized transfers, you need to use some of the other DSPLINK framework APIs, such as MSGQ'... - WC 09:21 AM Software Development: RE: PROC_read()
- Greg,
Can you clarify your answer with a bit more detail? Are you saying that the DSP should send a message to the ARM via IPC to hold off on accessing shared memory then send a follow-up message to indicate accessing memory is subseq...
12/19/2012
- GG 02:54 PM Software Development: RE: PROC_read()
- Hi Terrence,
What I've seen done here in situations like you are describing is to use the dsplink interfaces and send messages between the DSP and ARM to synchronize. In this way the DSP knows when it is safe to write and the ARM kno... - TL 02:45 PM Software Development: RE: PROC_read()
- To clarify. I am using Critical Link's API MityDSP::tcDspApp to load the DSP application, configure the shared memory region, and communicate with the DSP.
- I have a shared memory read issue between the ARM and DSP processor that I am trying to resolve. I am using PROC_read() function to copy data from DSP memory to a memory buffer used by the ARM. My question has to do with inter-processo...
12/18/2012
- CO 09:38 AM FPGA Development: RE: I2C issues on SLX45
- Further - I broke my OLED writes into < 32 bytes each and retested. That works fine and if it was unreliable, the pictures would show corruption which they don't. I can live with that! Thanks Mike.
I guess there two things for future ... - CO 08:54 AM FPGA Development: RE: I2C issues on SLX45
- Hi guys. Got a chance to test this today. That's a lot better! The i2cdetect scan picks up the device and shows "--" on non-existant devices just like it should. My i2ctemperature program reads out the ID and temperature properly now too...
- MW 09:00 AM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- The EMIFA DCM may not be required. If you do not require any other clocks than the 100 MHz (when running at 300 MHz CPU speed), then you can probably use a BUFG and skip the DCM.
The DCM does provide better skew management, but most ... - CO 08:32 AM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- Hmmm. Not sure now because I'm afraid I didn't use the DCM at all! I didn't connect the i_ema_clk directly but via a global net (a BUFG). This is what the Critical Link industrialio example does rather than use a DCM. Indeed, their examp...
- MC 08:13 AM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- Dear Conor,
I appreciate your help!
I have the suspect that the component emaclkdcm-Emifa_dcm is a digital clock manager of the emif clock, I'm not sure that I can eliminate it without pain.
Sure I will try not to include it in th... - CO 05:43 AM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- The learning curve for Xilinx tools is pretty darn steep anyway without jumping in at the deep end!
What *I* did is to add in the files I needed to my project starting with the top level VHDL file and the UCF file - I keep those in th...
12/17/2012
- Hello,
I'm working to a project with a MityOMAP-L138-FX-225-RC.
Currently, I try to use SYSBIOS into this module (ARM CPU part) with CCS environment.
I executed successfully some example (with task_delay) on the target using the ge... - MC 01:44 PM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- Dear Jean-Pierre,
I am a newbie too in fpga programming: could you please post me a suggestion about the solution?
I have the same inconvenience.:)
Thank you very much in advance!
Michele - CO 10:20 AM FPGA Development: RE: I2C issues on SLX45
- Scratch that - I see -DDEBUG is in the Makefile :)
- CO 10:17 AM FPGA Development: RE: I2C issues on SLX45
- No worries Mike. I used to be a QA guy so I must have a knack for finding these things! Like communicating with a non-existent device. I'd just finished doing the make so I made those changes and did make again. I'll add -DDEBUG in case ...
- MW 09:17 AM FPGA Development: RE: I2C issues on SLX45
- Hi Conor,
I am updateing (via editing) the patch on the previous post. We've finished some testing here and found a couple other bugs that should be cleaned up.
- Missed an additional read of that pesky done bit.
- Added a return...
12/16/2012
- CO 09:04 AM FPGA Development: RE: I2C issues on SLX45
- Thanks Mike, I looked at the driver code but wasn't really familiar enough with it to help. I was suspicious something was wrong codewise as the i2c driver was returning nonsense on the first read and then perfectly valid information on ...
12/14/2012
- MW 01:46 PM FPGA Development: RE: I2C issues on SLX45
- Hi Connor.
I think we may have found the issue. There may be a bug in the linux driver.
If you are OK recompiling the FPGA drivers on linux, can you please apply the following patch and see if the problems clear?
There was a mo...
12/11/2012
- MW 08:40 AM Software Development: RE: dsplinkk.ko compatibility
- I updated my instructions to clarify the commands on the last post...
-Mike
- MW 08:34 AM Software Development: RE: dsplinkk.ko compatibility
- If you added or removed features from the kernel, you may need to rebuild the dsplink drivers.
To do that:
# source the toolchain setup script like you did to build the kernel.
# cd to ${MDK}/sw/3rdparty/dsplink_linux_1_65_00_03/... - MC 08:09 AM Software Development: RE: dsplinkk.ko compatibility
- Michael Williamson wrote:
> There should be a dsplinkk.ko file in the /lib/modules/3.2.0/ directory in the reference filesystems. See http://support.criticallink.com/redmine/boards/10/topics/2068?r=2073#message-2073
> ...
Hello All,
...
12/06/2012
- TL 01:51 PM Software Development: RE: Linux DaVinci Video Port Interface (VPIF)
- My OMAP-L138 VPIF issue has been resolved! There was a conflict with PINMUX16 and PINMUX17 control register settings. The boards's LCD PINMUX settings were overriding the VPIF data out settings (i.e. disabling the VPIF DATAOUT[0-7] out...
- FT 12:25 PM Software Development: RE: Extremely slow root file system
- Thanks Mike for answer.
I forwarded your last comment to our HW engineer.
Chances are I will not get other questions from him. He is extremely busy theses days. I will create a new discussion thread if he comes back with other que... - MW 09:23 AM Software Development: RE: Extremely slow root file system
- The approach by your HW designer is fine.
Tri-stating the unused lines that are connected to the EMIFA and IRQ lines is really they key, but you need to explicitly do that in your code if you want to leave other pins as pulled down.... - FT 09:13 AM Software Development: RE: Extremely slow root file system
- Mike,
The unused I/O pins in our FPGA design seems to be the culprit.
Here a comment from our hardware engineer.
> It's actually not good to leave pins floating that are totally unused.
> ...
What do you think about that?
Th...
12/05/2012
- MW 03:22 PM Software Development: RE: Extremely slow root file system
- Please make sure that any unused IO pins on your FPGA design are "floating" and not "pulled-down" in the bitstream generation options of the Xilinx tools.
By default, unused I/Os are pulled-down. That can cause pins on the EMIFA bus ... - Hardware configuration: Industrial IO board + L138-DI-225-RI
We have a FPGA application that transmit data to DSP through uPP (16 bits configuration, channel A, data[0:15], start signal enabled, enable signal disabled).
Here pin mu... - CO 10:49 AM FPGA Development: RE: I2C issues on SLX45
- I dropped the drive strength to 6 on the SCL and SDA lines and it makes a slight difference - not so much ground bounce. The signals looks okish but communication is unreliable - almost as if the SDA read is being done right on the edge ...
- CO 07:20 AM FPGA Development: RE: I2C issues on SLX45
- (Busy writing reports instead of doing the work the reports are about!)
For drive strength I was using the Xilinx defaults - I'd never even thought about them before. According to Planahead, the SDA and SCL pins are drive strength 12....
12/04/2012
- MW 11:29 AM Software Development: RE: Linux DaVinci Video Port Interface (VPIF)
- Hi Terrence,
Sorry for the confusion. The linux kernels 2.6.X tracked TI's Platform Support Package releases from their arago site, not the mainline. TI has the tendency to rewrite their git history on those PSP branches (as much of... - TL 09:55 AM Software Development: RE: Linux DaVinci Video Port Interface (VPIF)
- I am currently using MDK_2011-12-05 DaVinici Linux kernel to support VPIF on a OMAP-L138F SoM platform. I attempted to use the newer MDK, MDK_2012-08-10, and I noticed that the MDK_2012-08-10 DaVinici Linux kernel does not provide VPIF ...
- I need to setup a VPIF interface (ala V4L2) using a Mity OMAP-L138F SoM platform running DaVinci Linux to support, BT.656, 8-bit, 720x480, composite (CVBS) video output only.
I have attempted to make customizations to the Linux kernel... - MW 07:12 AM FPGA Development: RE: I2C issues on SLX45
- Hi Conor,
What are you using for drive strength on the FPGA? You might be able to lower the drive strength if there is capacitance on the lines, but yeah, I would try a lower pullup value.
I am wondering if the I2C driver is not h... - CO 05:50 AM FPGA Development: RE: I2C issues on SLX45
- Hi again. It looks like the fpga is doing the right thing but the rise times are just too slow. Er. I guess that's my fault - should I lower the resistor values somewhat? I've captured the scope outputs from the ARM i2c bus and the FPGA ...
12/03/2012
- CO 10:26 AM FPGA Development: RE: I2C issues on SLX45
- Oh and 5K pull ups are to 3.3V on pin J701.38. SDA/SCL read 3.3V, at least on power on they do...
- CO 10:14 AM FPGA Development: RE: I2C issues on SLX45
- Thanks Mike. Sure it was evident the generics shouldn't be there and if they are it won't synthesise so it's not much a problem. I see the frequency set and the TODO! - makes more sense in the driver I guess. 200KHz is fine actually - it...
- MW 07:14 AM FPGA Development: RE: I2C issues on SLX45
- Hello Conor,
For the I2C, you are correct, the generics in the TOP were a carry over from a previous port -- should have caught that. The core is consistent with the package file, and the clock rate is controlled via a software progr... - Just one or two questions on the I2C ngc module. The industrialio_top.vhd example code uses a generic map to set clock rates. This seems out of sync with the MityDSP_L138_pkg.vhd package file which has no such maps. So I left them out. I...
- MW 08:31 AM Software Development: RE: Using RAM as temporary storage
- The 128 MB of Memory is total system memory. Some of it is used for the kernel and application space, but typically not all of it.
We have had some kernel and application foot prints as small as 12 MB, which would leave a larger chun... - MC 04:23 AM FPGA Development: RE: Pinout on L138-FG-225-RC
- Thank you Mike!
Another question: I see that you provide Bank 0 and Bank 1 of the FPGA on the SO-DIMM socket.
Am I free to use, for example, a GPIO Core across the banks, so connecting, for instance, a GPIO pin on a Bank 0 pin and an...
12/02/2012
- MW 02:59 PM FPGA Development: RE: Pinout on L138-FG-225-RC
- Hi Michele,
There is no issue if you are using 6SLX16 FPGAs in any module configuration.
This only a problem with 6SLX45 modules, as the issue is with the wire bonding on the LX45 FPGA chips in the package used by the modules. Cri... - MC 02:53 PM FPGA Development: RE: Pinout on L138-FG-225-RC
- Hello Tom,
the issue is (or was) on the datasheet of the SOM MityDSP
http://www.mitydsp.com/images/upload/File/MityDSP-L138F%20Spec.pdf
at page 7 you say that :
" The Xilinx 6SLX45 FPGA does not bond I/O Buffers to balls E7,... - TC 02:24 PM FPGA Development: RE: Pinout on L138-FG-225-RC
- Michele -
Can I ask for a reminder of what that issue is or a pointer to a forum post? I'm unable to locate it at the moment.
Thanks,
Tom - Hello All,
to be sure about the pinout of the SOM L138-FG-225-RC using the FPGA 6SLX16 , I ask if you fixed the issue on the pins 154 through 164 and 170-172.
I read that this applies to 6SLX45, and I want to be sure before making a cu...
11/30/2012
- Posting on behalf of a customer:
Customer wants to store data to the SD card but believes they will be bursting more than the write speeds that we have tested for the SD card interface (http://support.criticallink.com/redmine/projects...
11/29/2012
- JB 05:34 PM FPGA Development: RE: Xilinx design suite 14.2 and MDK_2012-08-10
- I found the solution!:)
- We've been using an OMAP-L138F SOM that has exhibited no problems until we re-flashed the section containing FPGA binary that loads at boot time (which we've done successfully multiple times.) Ever since we've updated that section of the...
- SM 11:16 AM Software Development: RE: Cannot Toggle GPIO pin
- Thanks for your speedy reply. I'm using 3.2 from the 2012-08-10 MDK.
- MW 11:14 AM Software Development: RE: Cannot Toggle GPIO pin
- Hi Spencer,
The issue is that the MCASP (see baseboard-industrialio.c) setup is configuring that pin to be in AFSR mode.
I will submit a patch to the 3.2 kernel (which one are you using?) to fix this, but a quick work around if you... - SM 11:04 AM Software Development: RE: Cannot Toggle GPIO pin
- Some funky formatting happened with the gpio name. Just for clarification its GPIO 0_13.
- I'm running a MitydspL138 on the Industrial IO board, and I'm trying to set GPIO[0]_13 via echoing directions and values to /sys/class/gpio13/. When I build the kernel against the industrialio_defconfig, I can set the direction to in or...
- ML 09:39 AM Software Development: RE: Problems building a rootfile system
- Mike,
You are right - it was a config problem. By comparing the config you attached with the default "industial io config" I was able to pin point the problem. In the "industial IO config" from git repository the "Plaform AHCI SATA s...
11/28/2012
- MW 01:51 PM Software Development: RE: Problems building a rootfile system
- Thanks for the information.
We have at least one active customer using the 3.2 kernel on an Industrial-IO board with Seagate SATA-II drive ("here":http://www.seagate.com/internal-hard-drives/laptop-hard-drives/momentus-thin/?sku=ST320... - ML 05:30 AM Software Development: RE: Problems building a rootfile system
- Hi,
Mike, thanks for your clarification.
I have two sata disks, one SSD which is sata-II (3.0gb) and one old mechanical drive which is sata-I (1.5gb). What I experience is:
*kernel 2.6.34 from git/SSD drive:*
ata1: SATA link u...
11/27/2012
- Hi all,
I am beginner with FPGA programming and want to develop a simple project on my MityDSP-l138F, involving only the the minimal set of components to toggle free FPGA gpios on an external bus I am not planning to use other buses lik... - MW 10:39 AM Software Development: RE: Problems building a rootfile system
- Hello,
I'm fairly certain that TI submitted the ahci-ti.c stuff originally in their PSP into the mainline and it got shuffled around a bit. That code is primarily platform specific and the driver folks wanted it out of the driver are... - ML 09:38 AM Software Development: RE: Problems building a rootfile system
- Hi,
Just compared the drivers/ata for kernel version 2.6.34 and 3.2. It seems obvious that the 3.2 branch is lacking a lot... The ahci-ti.c file is not even present in the 3.2 branch. Is there another branch which has this issue fixed...
11/26/2012
- KV 05:17 PM Software Development: RE: helloworld dsplink example
- Do not get a chance to exit the application.
here is the log:
root@mityomapl138:/#
root@mityomapl138:/#
root@mityomapl138:/# ./HelloWorldARM HelloWorldDSP.out
Loading file HelloWorldDSP.out
Msgq <debug> open: 0x00008000
PROC... - PS 02:49 PM Software Development: Building openembedded-core from scratch : MityDSP overlay breaks meta-toolchain-qte
- Hi,
Is there a fix yet for the broken build system?
Would it not be possible to move the open parts to a public repository?
Thanks
Phil
11/25/2012
- KF 02:34 PM Software Development: RE: GPIO Interrupt: request_irq() returning error: EINVAL
- Hi Mike,
You were correct - I had failed to use the gpio_to_irq() function.
It all works sweet now!
Thanks for you help,
Keith.
11/24/2012
- MW 07:59 PM Software Development: RE: helloworld dsplink example
- Are you exiting the application by hitting 'q'?
-Mike
- in Helloworld dsp link example, get follwing aserts! why?
root@mityomapl138:/# ./HellWorldARM HellWorldDSP.out
Loading file HellWorldDSP.out
Msgq <debug> open: 0x00008000
PROC Load successful
Starting application.
Msgq <GPPMSGQ1>... - MW 03:46 PM Software Development: RE: dsplinkk.ko compatibility
- There should be a dsplinkk.ko file in the /lib/modules/3.2.0/ directory in the reference filesystems. See http://support.criticallink.com/redmine/boards/10/topics/2068?r=2073#message-2073
There is a blurb about rebuilding the module ...