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Building Vivado Example Projects for MitySOM-AM57X

Each of the example projects provided by Critical Link includes a TCL script for building a reference Vivado GUI project as well as compiling them via the command line. Within each example folder, a README.md file should be present with instructions for generating the project and/or bitstream.

Example instructions are described on the Example Projects page.

FPGA bitstream generation / notes

In order to properly create a loadable bitstream from the uBoot prompt, you must convert the bitstream into a binary file targting Slave Select Map 8-bit parallel loading. The example command shown below outlines the typical arguments needed for programming an Artix-7 15 K logic element part:

write_cfgmem -force -format BIN -size 4 -interface SMAPx8 -loadbit "up 0 my_project_bitstream.bit" -verbose uboot_ready_bitstream.bin

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