SOM Video Input(VIP) from FPGA¶
Simulate a simple RGB color bar pattern at 1920 x 1080p with 24-bit RGB and embedded SYNCs for the AM57x. This is strictly following the ITU-R BT.1120-9 spec for sync codes and line timing. The goal of this is to test and demonstrate the MitySOM-AM57x / FPGA PORT A 24-bit VIP interface.
The FPGA VIP core is continuously sending a test pattern over the VIP interface after it is programmed. The following will capture a raw frame containing the 1920 x 1080p 24-bit RGB image that is a color bar test pattern. You can view this image using a raw image viewer.
yavta --skip 1 -c2 -fRGB24 -F -s1920x1080 /dev/video1 --file=frame.bin
NOTE The above command captures two frames and discards the first frame. Since the FPGA is continuously transmitting, the first frame may be corrupt until the FIFOs sync up.
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