Core Version Register for MitySOM-AM57X¶
The Core Version Register is common FPGA VHDL code that is used in all "standard" FPGA Cores for the MitySOM-AM57x framework.
The Core Version Register is generally located at the 0x00 (first) offset in a core address space. It is a 16-bit wide register that behaves like a circular FIFO or ring buffer. 4 reads of the register are required to access the complete contents of the register data. The table below lists the fields and the read cycle. The top 2 bits can be used to decode which read cycle contents are presented.
| Read Cycle | D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 00 | LVL | VEC | ID | ||||||||||||
| 1 | 01 | YEAR | VER_MAJ | VER_MIN | ||||||||||||
| 2 | 10 | 00 | MONTH | 000 | DAY | |||||||||||
| 3 | 11 | 0000000000 | NUM_VEC | |||||||||||||
Field Descriptions
| Field | Description |
|---|---|
| ID | an 8 bit core ID |
| VEC | the interrupt vector level (if used) |
| LVL | the interrupt level. 0 is for SYS_NIRQ1, 1 is for SYS_NIRQ2. |
| VER_MAJ | the Core major version number |
| VER_MIN | the Core minor version number |
| YEAR | the year, since 2000, of the last modification date of the core |
| MONTH | the month (1-12), of the last modification date of the core |
| DAY | the day (1-31), of the last modification date of the core |
| NUM_VEC | Number of vectors minus 1 so 0=1 vector, 1=2 vectors,... 0xF=0 vectors |
If multiple vectors are used, they are sequential where VEC specifies the lowest numbered vector.
Known FPGA IDs
This is a list of known FPGA IDs in the common / distributed IP cores. Users may define their own IDs for application specific projects.
| ID (dec) | Description |
|---|---|
| 4 | GPIO Core |
| 11 | ADS8343 4-channel ADC interface Core |
| 16 | ADS8344 8-channel ADC interface Core |
| 45 | ADS1274 Interface Core |
| 64 | Stream to PCIe DMA Core |
| 69 | PCIe DMA Control Core |
| 71 | Video Test Pattern Generator Core |
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